Timer Interrupt Status Register - Intsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[1] CH1CCG
[0] CH0CCG
Timer Interrupt Status Register – INTSR
This register stores the timer interrupt status.
Offset: 0x07C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
CH3OCF CH2OCF
Type/Reset RW 0 RW
Bits Field
[10] TEVIF
Rev. 1.00
Descriptions
Channel 1 Capture / Compare Generation
A Channel 1 capture / compare event can be generated by setting this bit. It is cleared
by hardware automatically.
0: No action
1: Capture / compare event is generated on channel 1
If Channel 1 is configured as an input, the counter value is captured into the
CH1CCR register and then the CH1CCIF bit is set. If Channel 1 is configured as an
output, the CH1CCIF bit is set.
Channel 0 Capture / Compare Generation
A Channel 0 capture / compare event can be generated by setting this bit. It is
cleared by hardware automatically.
0: No action
1: Capture / compare event is generated on channel 0
If Channel 0 is configured as an input, the counter value is captured into the
CH0CCR register and then the CH0CCIF bit is set. If Channel 0 is configured as an
output, the CH0CCIF bit is set.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CH1OCF CH0OCF
0 RW 0 RW
Descriptions
Trigger Event Interrupt Flag
This flag is set by hardware on a trigger event and is cleared by software.
0: No trigger event occurs
1: Trigger event occurs
236 of 486
27 26
Reserved
19 18
Reserved
11 10
TEVIF
RW 0
3 2
CH3CCIF CH2CCIF
0 RW 0 RW 0 RW
25 24
17 16
9 8
Reserved UEVIF
RW 0
1 0
CH1CCIF CH0CCIF
0 RW 0
July 31, 2018