Figure 46. Channel 2 And Channel 3 Input Stages; Figure 47. Ti0 Digital Filter Diagram With N = 2 - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
TI2
GT_CH2
Filter
f
sampling
TI2F
TI3
GT_CH3
Filter
f
sampling
TI3F

Figure 46. Channel 2 and Channel 3 Input Stages

Digital Filter
The digital filters are embedded in the input stage for the GT_CH0 ~ GT_CH3 pins respectively.
The digital filter in the GPTM is an N-event counter where N refers to how many valid transitions
are necessary to output a filtered signal. The N value can be 0, 2, 4, 5, 6 or 8 according to the user
selection for each filter.
Digital Filter (N=2)
TI0
D
CK
f
SYSTEM

Figure 47. TI0 Digital Filter Diagram with N = 2

Rev. 1.00
TRCED
f
CLKIN
TI2FP
TI2S2
TI2FN
CH2P
TI3S2
TI2S3
CH3P
TI3FP
TI3S3
TI3FN
Q D Q D Q
CK CK
f
sampling
198 of 486
CH2CCS
Edge TI2S2ED
Detection
CH2PRESCALER
Edge TI3S2ED
Detection
Edge
TI2S3ED
Detection
CH3PRESCALER
Edge
TI3S3ED
Detection
CH3CCS
No Filtered
CH2PSC
CH2CAP Event
CH2PSC
CH3PSC
CH3CAP Event
CH3PSC
J Q
Filtered
CK
K
July 31, 2018