Hardware Implementation-Dependent Register 0 - IBM PowerPC 604 User Manual

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The PIR can be accessed with the mtspr and mfspr instructions using the SPR number,
1013. Note that although this number is defined
by
the OBA, the register structure is defined
by
each implementation that implements this optional register.
2.1.2.3 Hardware Implementation-Dependent Register O
The hardware implementation dependent register 0 (HIDO) is an SPR that controls the state
of several functions within the 604.
Table 2-3. Hardware Implementation-Dependent Register O Bit Settings
Bit
Description
0
Enable machine che<:k i11>ut pin
0
The assertion of the
UC!'
does
not
cause a machine check exception.
1
Enables the entry into a machine check exception based on assertion of the
UC!'
input, detection of a
Cache Parity Error, detection ol an address parity error, or detection ol a data parity error.
Note that the machine check exception Is further affected by the MSR(ME] bit, which specifies whether the
processor checkstops or continues processing.
1 Enable cache parity checking
0
The detection of a cache parity error does not cause a machine check exception.
1
Enables the entry into a machine check exception based on the detection of a cache parity error.
Note that the machine check exception is further affected by the MSR(ME] bit, which specifies whether the
processor checkstops or continues processing.
2 Enable machine check on address bus parity error
0
The detection of a address
bus
parity error does not cause a machine check exception.
1 Enables the entry Into a machine check exception based on the detection of an address parity error.
Note that the machine check exception is further affected by the MSR(ME] bit, which
specifies
whether the
processor checkstops or continues processing.
3 Enable machine check on data
bus
parity error
0
The
detection of a data bus parity error does not cause a machine check exception.
1 Enables the entry into a machine check exception based on the detection of a data bus parity error.
Note that the machine check exception is further affected by the MSR(ME] bit, which specifies whether the
processor checkstops or continues processing.
7
Disable snoop response high state restore
HID bit
7,
if active, aHers bus protocol sfightly by preventing the processor from driving
the~
and
ARTF1V
signals to the high (negated) state.
H
this is done, then the system must restore the signals to the high state.
15
Not hard reset
0 A
hard reset occurred if software had previously set this bit
1 A hard reset has not occurred.
16 Instruction cache enable
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were marked
cache-inhbited (WIM
=
X1X).All
potential cache accesses from the bus (snoop, cache ops) are ignored.
1 The instruction cache is enabled
17
Data cache enable
0
The data cache
is
neither accessed nor updated.
All
pages are accessed as
H
they were marked
cache-inhbited (WIM
=
X1
X).
All
potential cache accesses from the bus (snoop, cache ops) are ignored.
1
The data cache
is
enabled.
2-10
PowerPC 604 RISC Microproceasor User's Manual