Description Of Pipeline Stages - IBM PowerPC 604 User Manual

Branch Instructions
Fetch Decode
Predict Predict
I<
?
I
Dispatch
Predict
Validate Complete
11111111111
Integer Instructions
Fetch Decode Dispatch Execute* Complete Write-Back
H < <I 11111111111
Load/Store Instructions
Fetch Decode
Floating-point Instructions
Dispatch
EA
Cale
Execute
Cache Align Complete Write-Back
"111111111111
Execute
Fetch Decode Dispatch
(Multiply)
(Add)
<Round Complete Write-Back
/Nbrmahze)
--=: · ·
11111111111
* Note that several integer instructions that execute in the MCIU have multiple execute stages.
Figure
6-4.
PowerPC 604 Microprocessor Pipeline Stages
Table 6-1 lists the latencies and throughputs for general groups of instructions.
Table 6-1. Execution Latencies and Throughputs
Instruction
Latency Throughput
Most integer instructions
1 1
Integer multiply (32x32)
4
2
Integer multiply (others) 3 1
Integer divide 20 19
Integer load 2 1
Floating-point load 3 1
Floating-point store 3 1
Double-precision floating-point multiply-add 3 1
Single-precision floating-point divide 18 18
Double-precision floating-point divide 31 31
6.2.1.1 Description of Pipeline Stages
This section gives a brief description of each of the six stages of the master instruction
pipeline.
Chapter 6. Instruction Timing
6-7