Address Transfer Signals; Address Bus (Ao-A31); Address Bus (Ao-A31}-0Utput (Memory Operations); Address Bus (Ao-A31)-Lnput (Memory Operations) - IBM PowerPC 604 User Manual

Timing Comments Assertion-Coincides with the assertion of ABB.
Negation-Occurs one bus clock cycle after the assertion of XATS.
High Impedance-Occurs one bus clock cycle after the negation of
XATS.
7.2.2.2.2 Extended Address Transfer Start (XATS)-lnput
Following are the state meaning and timing comments for the XATS input signal.
State Meaning Asserted-Indicates that the 604 must check for a direct-store
operation reply.
Negated-Indicates that there is no need to check for a direct-store
operation reply.
Timing Comments Assertion-May occur while ABB is asserted.
Negation-Must occur one bus clock cycle after XATS is asserted.
7 .2.3 Address Transfer Signals
The address transfer signals are used to transmit the address and to generate and monitor
parity for the address transfer. For a detailed description of how these signals interact, refer
to Section 8.3.2, "Address Transfer."
7 .2.3.1 Address Bus (AO-A31)
The address bus (AO-A31) consists of 32 signals that are both input and output signals.
7.2.3.1.1 Address Bus (AO-A31)-0utput (Memory Operations)
Following are the state meaning and timing comments for the AO-A31 output signals.
State Meaning Asserted/Negated-Represents the physical address (real address in
the architecture specification) of the data to be transferred. On burst
transfers, the address bus presents the double-word-aligned address
containing the critical code/data that missed the cache on a read
operation, or the first double word of the cache line on a write
operation. Note that the address output during burst operations is not
incremented. See Section 8.3.2, "Address Transfer."
Timing Comments Assertion/Negation-Occurs on the bus clock cycle after a qualified
bus grant (coincides with assertion of ABB and TS}.
High Impedance-Occurs one bus clock cycle after AACK is
asserted
7.2.3.1.2 Address Bus (AO-A31)-lnput (Memory Operations)
Following are the state meaning and timing comments for the AO-A31 input signals.
State Meaning Asserted/Negated-Represents the physical address of a snoop
operation.
Timing Comments Assertion/Negation-Must occur on the same bus clock cycle as the
assertion of TS; is sampled by 604 only on this cycle.
Chapter 7. Signal Descriptions 7-7