Instruction Cache Organization - IBM PowerPC 604 User Manual

The 16-Kbyte, four-way set data cache is nonblocking write-back cache with hardware
reload. The data cache can continue to process loads and stores while as many as four block
fill requests are in progress.
The set associativity of the data cache is shown in Figure 3-1.
Each cache block contains eight contiguous words from memory that are loaded from an
eight-word boundary (that is, bits A27-A31 of the EA are zero); as a result, cache blocks
are aligned with page boundaries. Within a single cycle, the data cache provides a double-
word access to the LSU.
The data cache supports a coherent memory system using the four-state MESI coherency
(modified/exclusive/shared/invalid) protocol. Dual-ported data cache tags are implemented
to prevent snooping accesses from affecting other bus traffic, except when snooping hits
modified data. The LSU is blocked for one cycle to copy the cache block of data into a
write-back buffer. The data cache can be invalidated on a block or invalidate-all granularity.
Also, data cache enable, lock, and parity checking enable bits can be set in hardware
implementation register 0 (HIDO).
3.2 Instruction Cache Organization
The 16-Kbyte, four-way set-associative instruction cache is physically-indexed. The
organization of the instruction cache, shown in Figure 3-1, is identical to that of the data
cache. Each cache block contains eight contiguous words from memory that are loaded
from an eight-word boundary (that is, bits A27-A31 of the effective addresses are zero); as
a result, cache blocks are aligned with page boundaries.
Within a single cycle, the instruction cache provides as many as four instructions to the
instruction fetch unit. The instruction cache coherency is software-controlled. The
instruction cache can be invalidated on a block or invalidate-all granularity. The instruction
cache can be enabled, locked, and checked for parity depending on the setting of enable bits
provided in HIDO.
The instruction cache differs from the data cache in that it does not implement MESI cache
coherency protocol, and a single state bit is implemented that indicates only whether a
cache block is valid or invalid. If a processor modifies a memory location that may be
contained in the instruction cache, software must ensure that memory updates are visible to
the instruction fetching mechanism. This can be achieved by the following instruction
sequence:
3-4
dcbst
sync
lcbl
sync
lsync
# update memoiy
# wait for update
# remove (invalidate) copy in instruction cache
# wait for ICBI operation
to
be globally pelfonned
# remove copy in own instruction buffer
PowerPC 604 RISC Microprocessor User's Manual