Floating-Point Instructions; Floating-Point Arithmetic Instructions - IBM PowerPC 604 User Manual

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Multiple-precision shifts can be programmed as shown in Appendix C, "Multiple-Precision
Shifts," in
The Programming Environments Manual.
The integer shift instructions are
summarized in Table 2-13.
Table 2-13. Integer Shift Instructions
Name Mnemonic Operand Syntax
Shift Left Word
slw (slw.) rA,rS,rB
Shift Right Word
SIW (SIW.)
rA,rS,rB
Shift Right Algebraic Word Immediate srawl (srawl.) rA,rS,SH
Shift Right Algebraic Word
sraw (sraw.)
rA,rS,rB
2.3.4.2 Floating-Point Instructions
This section describes the floating-point instructions, which include the following:
• Floating-point arithmetic instructions
• Floating-point multiply-add instructions
• Floating-point rounding and conversion instructions
• Floating-point compare instructions
• Floating-point status and control register instructions
• Floating-point move instructions
See Section 2.3.4.3,
"Load
and Store Instructions," for information about floating-point
loads and stores.
The PowerPC architecture supports a floating-point system as defined in the IEEE 754
standard, but requires software support to conform with that standard. All floating-point
operations conform to the IEEE 754 standard, except
if
software sets
the
non-IEEE mode
bit
(NI)
in the FPSCR.
2.3.4.2.1 Floating-Point Arithmetic Instructions
The floating-point arithmetic instructions are summarized in Table 2-14.
Table 2·14. Floating-Point Arithmetic Instructions
Name
Mnemonic Operand Syntax
Floating Add (Double-Precision) fadd (fadd.) frD,frA,frB
Floating Add Single fadds (fadds.)
frD,frA,frB
Floating Subtract (Dolble-Precision) fsub (fsub.)
frD,frA,frB
Floating Subtract Single
fsubs (fsubs.)
frD,frA,frB
Floating Multiply (Dolble-Precision) fmul (fmul.)
frD,frA,frC
Floating Multiply Single fmuls (fmuls.) frD,frA,frC
Floating Divide (Double-Precision) fdlv (fdlv.)
frD,frA,frB
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