IBM PowerPC 604 User Manual page 170

Table 4-1. Exception Classlflcatlons
Type
Exception
Asynchronouslnonmaskable
Machine Check
SystemR8S8t
Asynchronoustmaskable External interrupt
Decrementer int&"""
System management inte1'1'14't (604-specific)
Performance monitoring exception (604-specific)
Synchronous/precise Instruction-caused exceptions
Synchronous/imprecise Instruction-caused imprecise exceptions
(Floating-point Imprecise exceptions)
Exceptions implemented
in
the 604, and conditions
that
cause them, are listed
in
Table 4-2.
Table 4-2. Exceptions and Conditions-Overview
Exception Vector onset
Causing Conditions
Type
(hex)
Reserved 00000
-
System r8S8t 00100 The causes of system reset exceptions are implementation-dependent. In the
604 a system reset Is caused by the assertion of either the soft reset or hard
reset signal.
If the conditions that cause the exception also cause the processor state
to be
corrupted such that the contents of SARO and SRR1 are no longer valid or such
that other processor resources are so corrupted that the processor cannot
reliably resume execution, the copy of the RI bit copied from the MSR to SRR1
lsdeared.
Machine check 00200
On the 604 a machine check exception is signaled by the assertion of a qualHied
TEA
indication on the 604 bus, or the machine check input
(~)
signal. If the
MSR[ME] is deared, the processor enters the checkstop state when one of
these signals is asserted. Note that MSR(ME] is cleared when an exception is
taken. The machine check exception is also caused by parity errors on the
address or data bus or in the instruction or data caches.
The assertion of the
TEA
signal is detennined by read, write, and instruction
fetch operations initiated by the processor; however,
it
is expected that the
TEA
signal would be used by a memory controller to indicate that a memory parity
error or an uncorrectable memory ECC error has occurred.
Note that the machine check exception is imprecise with respect to the
instruction that originated the bus operation.
The machine check exception Is disabled when MSR(ME]
=
0. If a machine
check exception condition exists and the ME bit is deared, the processor goes
into the checkstop state. (Note that, physical address is referred to as the real
address in the architecture specification.)
If the conditions that cause the exception also cause the processor state to be
corrupted such that the contents of SARO and SRR1 are no longer valid or such
that other processor resources are so corrupted that the processor cannot
reliably resume execution, the copy of the RI bit copied from the MSR to SRR1
is cleared.
Chapter 4. Exceptions 4-3