Data Cache Coherency Protocol; Mesi State Definitions - IBM PowerPC 604 User Manual

These attributes are programmed ·by the operating system for each page and block. The W
and I attributes control how the processor performing an access uses its own cache. The
M attribute ensures that coherency is maintained for all copies of the addressed memory
location. The G attribute prevents speculative loading and prefetching from the addressed
memory location.
3.6.1 Data Cache Coherency Protocol
Each 32-byte cache block in the 604 data cache is in one of four states. Addresses presented
to the cache are indexed into the cache directory and are compared against the cache
directory tags. If no tags match, the result is a cache miss. If a tag match occurs, a cache hit
has occurred and the directory indicates the state of the block through three state bits kept
with the tag.
The four possible states for a block in
the
cache are the invalid state
(I),
the shared state (S),
the exclusive state (E), and the modified state
(M).
The four MESI states are defined in
Table 3-3 and illustrated in Figure 3-5.
Table 3-3. MESI State Definitions
MESI State
Definition
Modified (M)
The addressed block is valid in the cache and in only this cache. The block is modified with respect
to system memory-that is, the modified data in the block has not been written
back
to memory.
Exclusive (E) The addressed block is in this cache only. The data in this block is consistent with system memory.
Shared (S)
The addressed bbck is valid in the cache and in at least one other cache. This block is always
consistent with system memory. That is, the shared state Is shared-unmodilled; there is no shared-
modilled
state.
Invalid (I) This
state
Indicates that the addressed block Is not resident in the cache and/or any data contained
Is considered not useful.
The primary objective of a coherent memory system is to provide the same image of
memory to all processors in the system. This is an important feature of multiprocessor
systems since it allows for synchronization, task migration, and the cooperative use of
shared resources. An incoherent memory system could easily produce unreliable results
depending on when and which processor executed a task. For example, when a processor
performs a store operation, it is important that the processor have exclusive access to the
addressed block before the update is made. If not, another processor could have a copy of
the old (or stale)
data.
Two processors reading from the same memory location would get
different answers.
To maintain a coherent memory system, each processor must follow simple rules for
managing the state of
the
cache. These include externally broadcasting the intention to read
a cache block not in the cache and externally broadcasting the intention to write into a block
that is not owned exclusively. Other processors respond to these broadcasts by snooping
their caches and reporting status back to the originating processor. The status returned
includes a shared indicator (that is, another processor has a copy of the addressed block)
Chapter 3. Cache and Bus Interface Unit Operation 3-11