Page History Recording - IBM PowerPC 604 User Manual

This section highlights those areas of the memory segment model defined by the OEA that
are specific to the 604.
5.4.1 Page History Recording
Referenced (R) and changed (C) bits reside in each PTE to keep history information about
the page. They are maintained by a combination of the 604 table search hardware and the
system software. The operating system uses this information to determine which areas of
memory to write back to disk when new pages must
be
allocated in main memory.
Referenced and changed recording is performed only for accesses made with page address
translation and not for translations made with the BAT mechanism or for accesses that
correspond to direct-store (T
=
1) segments. Furthermore, Rand C bits are maintained only
for accesses made while address translation is enabled (MSR[IR] = 1 or MSR[DR] = 1).
In the 604, the referenced and changed bits are updated as follows:
• For TLB hits, the C bit is updated according to Table 5-7.
• For TLB misses, when a table search operation is in progress to locate a PTE. The
R and C bits are updated (set,
if
required) to reflect the status of the page based on
this access.
Table 5·7. Table Search Operations to Update History Blts-TLB Hit case
RandCbHs
Processor Action
lnTLB Entry
00 Combination doesn't occur
01 Combination doesn't occur
10 Read: No special action
Write: The 604 initiates a table search operation to
~ate
C.
11 No special action for read or write
The table shows that the status of the C bit in the TLB entry (in the case of a TLB hit) is
what causes the processor to update the C bit in the PTE (the R bit is assumed to be set in
the page tables
if
there is a TLB hit). Therefore, when software clears the R and C bits in
the page tables in memory, it must invalidate the TLB entries associated with the pages
whose referenced and changed bits were cleared.
The debt and dcbtst instructions can execute if there is a TLB/BAT hit or if the· processor
is in real addressing mode. In case of a TLB/BAT miss, these instructions are treated as
no-ops; they do not initiate a table search operation and they do not set either the R or C bits.
As defined by the PowerPC architecture, the referenced and changed bits are updated as
if
address translation were disabled (real addressing mode). Additionally, these updates are
performed with single-beat read and byte write transactions on the bus.
Chapter 5. Memory Management
5-21
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