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The floating-point pipeline has three stages. Floating-point divide operations iterate in the
first stage.
1.4 Power Management-Nap Mode
The 604 provides a power-saving mode, called nap mode, in which all internal processing
and bus operations are suspended Software initiates nap mode by setting the MSR[POW]
bit. After this bit is set, the 604 suspends instruction dispatch and waits for all activity in
progress, including active and pending bus transactions, to complete. It then powers down
the internal clocks, and indicates nap mode by asserting the HALTED output signal.
When the 604 is in nap mode, all internal activity stops except for decrementer, time base,
and interrupt logic, and the 604 does not snoop bus activity unless the system asserts the
RUN input signal. Asserting the RUN signal causes the HALTED signal to be negated.
Nap mode is exited (clocks resume and MSR[POW] cleared) when any asynchronous
interrupt is detected.
1.5 Performance Monitor
The 604 incorporates a performance monitor facility that system designers can use to help
bring up, debug, and optimize software performance, especially in multiprocessing
systems. The performance monitor is a software-accessible mechanism that provides
detailed information concerning the dispatch, execution, completion, and memory access
of PowerPC instructions.
The monitor mode control register 0 (MMCRO) can be used to specify the conditions for
which a performance monitoring interrupt is taken. For example, one such condition is
associated with one of the counter registers (PMCl or PMC2) incrementing until the most
significant bit indicates a negative value. Additionally, the sampled instruction address and
sampled data address registers (SIA and SDA) are used to hold addresses for instruction
and data related to the performance monitoring interrupt.
Chapter 1. Overview
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