IBM PowerPC 604 User Manual page 11

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Number
4.5.13
4.5.14
4.5.15
4.5.16
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.6.1
5.1.6.2
5.1.6.3
5.1.6.4
5.1.7
5.1.8
5.1.9
5.2
5.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.4.3
5.4.3.1
5.4.3.2
5.4.4
5.4.5
5.4.6
5.4.7
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
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CONTENTS
Title
Page
Number
Perfonnance Monitoring Interrupt (OxOOFOO) ............................................... 4-20
Instruction Address Breakpoint Exception (Ox01300) .................................. 4-20
System Management Interrupt (Ox01400) ..................................................... 4-20
Power Management ....................................................................................... 4-21
Chapter 5
Memory Management
MMU Overview ................................................................................................... 5-2
Memory Addressing ........................................................................................ 5-4
MMU Organization .......................................................................................... 5-4
Address Translation Mechanisms .................................................................... 5-9
Memory Protection Facilities ......................................................................... 5-11
Page History Infonnation ................................................................................ 5-12
General Flow of MMU Address Translation ................................................. 5-12
Real Addressing Mode and Block Address Translation Selection ............ 5-12
Page and Direct-Store Interface Address Translation Selection ............... 5-14
Selection of Page Address Translation ....................................................... 5-16
Selection of Direct-Store Interface Address Translation ........................... 5-16
MMU Exceptions Summary .......................................................................... 5-16
MMU Instructions and Register Summary .................................................... 5-18
TLB Entry Invalidation .................................................................................. 5-19
Real Addressing Mode ....................................................................................... 5-20
Block Address Translation ................................................................................. 5-20
Memory Segment Model ................................................................................... 5-20
Page History Recording ................................................................................. 5-21
Referenced Bit ........................................................................................... 5-22
Changed Bit ............. , ................................................................................. 5-22
Scenarios for Referenced and Changed Bit Recording ............................. 5-23
Page Memory Protection ............................................................................... 5-24
TLB Description ............................................................................................ 5-24
TLB Organization ...................................................................................... 5-24
TLB Invalidation ....................................................................................... 5-26
Page Address Translation Summary .............................................................. 5-27
Page Table Search Operation ......................................................................... 5-29
Page Table Updates ....................................................................................... 5-33
Segment Register Updates ............................................................................. 5-34
Direct-Store Interface Address Translation ....................................................... 5-35
Direct-Store Interface Accesses ..................................................................... 5-35
Direct-Store Segment Protection ................................................................... 5-35
Instructions Not Supported in Direct-Store Segments ................................... 5-36
Instructions with No Effect in Direct-Store Segments .................................. 5-36
Direct-Store Segment Translation Summary Flow ........................................ 5-36
PowerPC 604 RISC Microprocessor User's Manual