IBM PowerPC 604 User Manual page 344

Figure 8-18 shows three ways
to
delay single-beat reads showing data-delay controls:
• The TA signal can remain negated to insert wait states in clock cycles 3 and 4.
• For the second access,
DBG
could have been asserted in clock cycle 6.
• In the third access, DRTRY is asserted in clock cycle 11
to
flush the previous data.
Note that all bidirectional signals are three-stated between bus tenures.
1112 31415
6
I
7
I
s
9
I
10
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11
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12
I
13
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14
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14
Figure 8-18. Slngle-Beat Reads Showing Data-Delay Controls
8-34
PowerPC 604 RISC Microprocessor Uaer's Manual