Floating-Point Move Instructions; Load And Store Instructions - IBM PowerPC 604 User Manual

2.3.4.2.6 Floating-Point Move Instructions
Floating-point move instructions copy data from one FPR to another.
The
floating-point
move instructions do not modify the FPSCR. The CR update option in these instructions
controls the placing of result status into CRl. Table 2-19 summarizes the floating-point
move instructions.
Table 2·19. Floatlng-Polnt Move Instructions
Name Mnemonic Operand Syntax
Floating Move Register tmr (fmr.) frD,trB
Floating Negate
tneg (tneg.) trD,frB
Floating Absolute Value
tabs (tabs.)
trD,frB
Floating Negative Absolute Value tnabs (tnabs.) trD,frB
2.3.4.3 Load and Store Instructions
Load and store instructions are issued and translated in program order; however, the
accesses can occur out of
order.
Synchronizing instructions are provided to enforce strict
ordering. This section describes the load and store instructions, which consist of the
following:
• Integer load instructions
• Integer store instructions
• Integer load and store with byte reverse instructions
• Integer load
and
store multiple instructions
• Floating-point load instructions
• Floating-point store instructions
• Memory synchronization instructions
Implementation Notes-The following describes how the 604 handles misalignment:
• If an unaligned memory access crosses a 4-Kbyte page boundary, within a normal
segment, an exception may occur when the boundary is crossed (that is, a protection
violation occurs on the new page). In these cases, the 604 triggers a OSI exception
and the instruction may have partially completed.
• Some misaligned memory accesses suffer performance degradation as compared to
an aligned access of the same
type.
Memory accesses that cross a word boundary are
broken into multiple discrete accesses by the load/store unit, except floating-point
doubles aligned on a double-word boundary. Any noncacheable access that crosses
a double-word boundary is broken into multiple external bus tenures.
Chapter 2. PowerPC 604 Processor
Programming
Model 2-33
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