Integer Load And Store Multiple Instructions - IBM PowerPC 604 User Manual

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In the 604, executing one of these invalid instruction forms causes CRO to
be
set to an
undefined value.
Table 2-22. Integer Load and Store with Byte Reverse Instructions
Name Mnemonic
Operand Syntax
Load Half Word Byte-Reverse Indexed lhbrx rD,rA,rB
Load Word Byte-Reverse Indexed lwbrx rD,rA,rB
Store Half Word Byte-Reverse Indexed sthbrx rS,rA,rB
Store Word Byte-Reverse Indexed stwbrx rS,rA,rB
2.3.4.3.6 Integer Load and Store Multiple Instructions
The load/store multiple instructions are used to move blocks of data to and from the GPRs.
The load multiple and store multiple instructions may have operands that require memory
accesses crossing a 4-Kbyte page boundary. As a result, these instructions may be
interrupted by a DSI exception associated with the address translation of the second page.
Implementation Notes-The following describes the 604 implementation of the
load/store multiple instruction:
• The PowerPC architecture requires that memory operands for Load Multiple and
Store Multiple instructions (lmw and stmw) be word-aligned. If the operands to
these instructions are not word-aligned, an alignment exception occurs. The 604
provides hardware support for lmw, stmw, lswi, lswx, stswi, and stswx instructions
to cross a page boundary. However, a OSI exception may occur when the boundary
is crossed (for example, if a protection violation occurs on the new page).
• Executing an lmw instruction in which rA is in the range of registers to be loaded
or in which RA= RT= 0 is invalid in the architecture. In the 604, all registers loaded
are set to undefined values. Any exceptions resulting from a memory access cause
the system error handler normally associated with the exception to be invoked.
• The 604's implementation of the lmw instruction allows one word of data to be
transferred
to
the GPRs per internal clock cycle (that is, one register is filled per
clock) whenever the data is found in the cache. For the stmw instruction, data is
transferred from the GPRs to the cache at a rate of one word (GPR) per clock cycle.
• When an lmw or stmw access is to noncacheable memory, data is transferred on the
external bus at a rate of one word per external bus tenure. Bus tenures are pipelined,
allowing a maximum tenure rate of one address tenure every three bus-clock cycles.
• The load multiple and load string instructions can be interrupted after the instruction
has partially completed If r A has been modified and the instruction is restarted, the
instruction begins loading from the addresses specified by the new value of rA,
which might be anywhere in memory; therefore, the system error handler may
be
invoked
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PowerPC 604 RISC Microprocessor User's Manual