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IBM MPC603EC User Manual

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MPR603HSU-03
(IBM Order Number)
Advance Information
PowerPC 603
Hardware Specifications
The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of
reduced instruction set computer (RISC) microprocessors. This document contains
pertinent physical characteristics of the 603. For functional characteristics of the processor,
refer to the PowerPC 603 RISC Microprocessor User's Manual.
This document contains the following topics:
Topic
In this document, the term "603" is used as an abbreviation for the phrase, "PowerPC 603
Microprocessor." The PowerPC 603 microprocessors are available from Motorola as
MPC603 and from IBM as PPC603.
The PowerPC name, PowerPC logotype, PowerPC Architecture, and PowerPC 603 are trademarks of International Business Machines Corp.
used by Motorola under license from International Business Machines Corp.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
change or discontinue this product without notice.
©
©
Instruction set and other portions
International Business Machines Corp. 1991-1995
RISC Microprocessor
™
MPC603EC/D
(Motorola Order Number)
5/95
REV 2
™
Page
2
4
4
14
15
17
21
26
27

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  • Page 1: Table Of Contents

    MPR603HSU-03 MPC603EC/D (IBM Order Number) (Motorola Order Number) 5/95 REV 2 ™ Advance Information PowerPC 603 RISC Microprocessor ™ Hardware Specifications The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical characteristics of the 603.

  • Page 2: Section 1.1, "Overview

    1.1 Overview The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC microprocessors. The 603 implements the 32-bit portion of the PowerPC Architecture™ specification, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
  • Page 3 • Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754-compliant FPU for both single- and double-precision operations — LSU for data transfer between data cache and GPRs and FPRs —...

  • Page 4: Section 1.2, "General Parameters

    1.2 General Parameters The following list provides a summary of the general parameters of the 603. µ Technology CMOS (four-layer metal) Die size 11.5 mm x 7.4 mm Transistor count 1.6 million Logic design Fully-static Max. internal frequency 80 MHz Max.
  • Page 5 Table 3 provides the DC electrical characteristics for the 603. Table 3. DC Electrical Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T ≤ 105 ° C Characteristic Symbol Unit Input high voltage (all inputs except SYSCLK) V IH Input low voltage (all inputs except SYSCLK) V IL...

  • Page 6: Ac Electrical Characteristics

    Table 4. Power Dissipation (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T ≤ 105 ° C Bus Frequency (SYSCLK) CPU Clock: Unit SYSCLK 25 MHz 33 MHz 40 MHz 50 MHz 66 MHz Nap Mode Typical Typical...
  • Page 7 Table 5. Clock AC Timing Specifications (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T ≤ 105 °C 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 Characteristic Unit Notes ± 150 ±...
  • Page 8 Table 6. Input AC Timing Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T ≤ 105 °C 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 MHz Unit Characteristic Notes Address/data/transfer — — —...
  • Page 9 SYSCLK ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 2. Input Timing Diagram HRESET MODE PINS VM = Midpoint Voltage (1.4 V) Figure 3. Mode Select Input Timing Diagram 1.3.2.3 Output AC Specifications Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
  • Page 10 Table 7. Output AC Timing Specifications (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C L = 50 pF, 0 ≤ T ≤ 105 °C 33.33 66.67 Characteristic Unit Notes SYSCLK to output — 16.0 —...
  • Page 11 SYSCLK ALL OUTPUTS (Except TS, ABB DBB, ARTRY) ABB, DBB ARTRY VM = Midpoint Voltage (1.4 V) Figure 4. Output Timing Diagram 603 Hardware Specifications, REV 2 Preliminary—Subject to Change without Notice...
  • Page 12 1.3.3 JTAG AC Timing Specifications Table 8 provides the JTAG AC timing specifications. Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C L = 50 pF, 0 ≤ T ≤...
  • Page 13 Figure 6 provides the TRST timing diagram TRST Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. Data Inputs Input Data Valid Data Outputs Output Data Valid Data Outputs Data Outputs Output Data Valid Figure 7. Boundary-Scan Timing Diagram Figure 8 provides the test access port timing diagram.

  • Page 14: Section 1.4, "Pinout Diagram

    1.4 Pinout Diagram Figure 9 contains the pin assignments for the 603. OGND OVDD OVDD OGND TOP VIEW OGND OVDD OVDD OGND DBWO DRTRY AACK DBDIS QREQ XATS ARTRY OGND OVDD OVDD OGND OGND OVDD OVDD OGND DL23 DL24 OGND OVDD OVDD OGND...

  • Page 15: Section 1.5, "Pinout Listing

    1.5 Pinout Listing Table 9 provides the pinout listing for the 603. Table 9. PowerPC 603 Microprocessor Pinout Listing Signal Name Pin Number Active A0–A31 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, High 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, AACK Input...
  • Page 16 Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued) Signal Name Pin Number Active HRESET Input Input LSSD_MODE Input L1_TSTCLK — Input L2_TSTCLK — Input Input OGND 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, Input 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 OVDD 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104,...

  • Page 17: Section 1.6, "Package Description

    Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued) Signal Name Pin Number Active TT0–TT4 191, 190, 185, 184, 180 High 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, High Input 167, 177, 207 Output XATS Notes: 1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation. 2.
  • Page 18 1.6.1.2 Mechanical Dimensions of the Motorola Wire-Bond CQFP Package Figure 10 shows the mechanical dimensions for the wire-bond CQFP package. θI –H– θ2 *Reduced pin count shown for clarity. 60 pins per side Min. Max. 30.86 31.75 34.6 BSC 3.75 4.15 0.5 BSC 0.18...
  • Page 19 1.6.2 IBM C4-CQFP Package Description The following sections provide the package parameters and mechanical dimensions for the IBM C4-CQFP package. 1.6.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack.
  • Page 20 1.6.2.2 Mechanical Dimensions of the IBM C4-CQFP Package Figure 11 shows the mechanical dimensions for the C4-CQFP package. Epoxy Dam Solder-Bump Encapsulant Chip Jmin Urethane Clip Leadframe Tape Cast Ceramic Cmax 0.08 0.13 TOTAL s *Reduced pin count shown for clarity. 60 pins per side Min.

  • Page 21: Section 1.7, "System Design Information

    1.7 System Design Information This section provides electrical and thermal design recommendations for successful application of the 603. 1.7.1 PLL Configuration A 603 part number corresponds to a particular combination of internal (CPU core) and SYSCLK (external bus) frequency ranges which the device has been tested to. The PLL is configured by the PLL_CFG0–PLL_CFG3 pins.
  • Page 22 1.7.2 PLL Power Supply Filtering The AVdd power signal is provided on the 603 to provide power to the clock generation phase-lock loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 12.
  • Page 23 Figure 13 provides a thermal management example for the Motorola wire-bond CQFP package. Motorola Wire-Bond CQFP With Heat Sink Forced Convection (m/sec) Figure 13. Motorola Wire-Bond CQFP Thermal Management Example The junction temperature can be calculated from the junction-to-ambient thermal resistance, as follows: Junction temperature: T θja + (R...
  • Page 24 Notes: 1. Junction-to-ambient thermal resistance is based on measurements on single-sided printed circuit boards per SEMI (Semiconductor Equipment and Materials International) G38-87 in natural convection. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. The vendors who supply heat sinks are Aavid Engineering, IERC, Thermalloy, and Wakefield Engineering.
  • Page 25 Figure 14 provides a thermal management example for the IBM C4-CQFP package. IBM C4-CQFP Exposed Die Aluminum Plate Pinfin 0.25 Forced Convection (m/sec) Figure 14. IBM C4-CQFP Thermal Management Example ° For a power dissipation of 2.5 Watts in an ambient temperature of 40 C at 1 m/sec with the pinfin heat sink measured above, the junction temperature of the device would be as follows: θja...

  • Page 26: Section 1.8, "Ordering Information

    1.8 Ordering Information This section provides the ordering information for the 603. Note that the individual part numbers correspond to a specific combination of 603 internal/bus frequencies, which must be observed to ensure proper operation of the device. For other frequency combinations, temperature ranges, power-supply tolerances package types, etc., contact your local Motorola or IBM sales office.

  • Page 27: Appendix A General Handling Recommendations For The Ibm Package

    Appendix A General Handling Recommendations for the IBM Package The following list provides a few guidelines for package handling: • Handle the electrostatic discharge sensitive (ESD) package with care before, during, and after processing. • Do not apply any load to exceed 3 Kg after assembly. •...
  • Page 28 A.2 Card Assembly Recommendations This section provides recommendations for card assembly process. Follow these guidelines for card assembly. • This component is supported for aqueous, IR, convection reflow, and vapor phase card assembly processes. The temperature of packages should not exceed 220 °C for longer than 5 minutes. •...
  • Page 29 Clean after reflow De-ionized (D.I.) water if water-soluble paste is used •Cleaner requirements—conveyorized, in-line •Minimum of four washing chambers —Pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 °C minimum, dwell time of 24 seconds minimum, water is not re-used, water flow rate of 30 liters/minute.

  • Page 30: Motorola Inc

    Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document.

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