IBM PowerPC 604 User Manual page 62

Table 1-2. Overview of Exceptions and Conditions (Continued)
Exception Vector Offset
Causing Conditions
Type
(hex)
OSI 00300 The cause of a OSI exception can be detennined by the bit settings in the
OSISR, listed as follows:
O Set if a load or store instruction resutts in a direct-store program exception;
otherwise cleared.
1 Set
if the translation of an attempted access is not found in the primary table
entry group (PTEG), or in the secondary PTEG, or in the range of a BAT
register; otherwise cleared.
4
Set
if a memory access is not permitted by the page or BAT protection
mechanism; otherwise cleared.
5 H SR[T]
=
1, set by an eclwx, ecowx, lwarx, or stwcx. instruction; otherwise
cleared. Set by an eclwx or ecowx instruction if the access is to an address
that is marked as write-through.
6
Set
for a store operation and cleared for a load operation.
9
Set
if an EA matches the address in the OABR while in one ol the three
compare modes.
1 O Set if the segment table search fails to find a translation for the effective
address; otherwise cleared.
11 Set if eclwx or ecowx is used and EAR[E] is cleared.
ISi 00400
An ISi exception is caused when an instruction fetch cannot be performed for
any of the following reasons:
.
The effective address cannot be translated. That is, there is a page fault for
this portion of the translation, so an ISi exception must be taken to retrieve
the translation from a storage device such as a hard disk drive.
.
The fetch access is to a direct-store segment .
.
The fetch access violates memory protection. H the key bits
(Ks
and Kp) in
the segment register and the PP bits in the PTE or BAT are set to prohbit
read access, instructions cannot be fetched from this location.
External 00500 An external interrupt occurs when the external exception signal,
lRT,
is
interrupt
asserted. This signal is expected to remain asserted untH the exception handler
begins execution. Once the signal is detected, the 604 stops dispatching
instructions and waits for all dispatched instructions to complete. Any
exceptions associated with dispatched instructions are taken before the
interrupt is taken.
Alignment
00600 An alignment exception is caused when the processor cannot perform a
memory access for the following reasons:
A floating-point load, store, lmw, stmw, lwarx, stwcx., eclwx, or ecowx
instruction is not word-aligned.
A dcbz instruction refers to a page that is marked either cache-inhbited or
write-through.
A dcbz instruction has executed when the 604 data cache is locked or disabled.
An access is not naturally aligned in little-endian mode.
An lmw, stmw, lswl, lswx, stswl, or stswx instruction is issued in little-endian
mode.
Chapter 1. Overview 1-31