Mmus/Bus Interface Unit - IBM PowerPC 604 User Manual

These operations are necessary because the data cache is a write-back cache. Because
instruction fetching bypasses the data cache, changes made to items in the data cache may
not be reflected in memory until after a fetch operation completes.
3.3 MMUs/Bus Interface Unit
The bus interface unit (BIU) is compatible with those of the PowerPC 601 ™ and
PowerPC 603™ microprocessors. It implements both tenured and split-transaction modes
and can handle as many as three outstanding transactions in pipelined mode. If permitted,
the BIU can complete one or more write transactions between the address and data tenures
of a read transaction. The BIU has 32-bit address and 64-bit data buses protected by byte
parity.
The BIU implements the critical-double-word-first access where the double word requested
by the fetcher or the LSU is fetched first and the remaining words in the line are fetched
later. The critical double word as well as other words in the cache block are forwarded to
the fetcher or to the LSU before they are written to the cache.
The bus can be run at lx, 2/3x, l/2x or l/3x the speed of the processor. The programmable
on-chip phase-locked loop (PLL) generates the necessary processor clocks from the bus
clock.
When a memory access fails to hit in the cache, the 604 accesses system memory through
the bus interface unit. These operations must arbitrate for bus access.
The memory management units (MMUs) provide address translation as specified by the
PowerPC OEA, including block address translation and page translation of memory
segments. The MMUs and the bus interface unit are shown in Figure 3-3.
The 604 implements separate MMUs, one for instruction accesses and one for data
accesses. Vrrtual address translation uses two 128-entry, two-way set-associative (64 x 2)
translation lookaside buffers (TLBs), one for instruction accesses and one for data accesses.
The 604 provides hardware that performs the TLB reload (also known as page table walk)
when a translation is not in a TLB. Memory management is described in Chapter 5,
"Memory Management."
The BIU handles block fill and write-back requests from either cache, as well as all
noncacheable reads and writes.
Chapter 3. Cache and Bus Interface Unit Operation 3-5