IBM PowerPC 604 User Manual page 70

-
The PowerPC's user-level registers are described as follows:
2-4
• User-level registers (UISA)-The user-level registers can be accessed by all
software with either user or supervisor privileges. The user-level register set
includes the following:
- General-purpose registers (GPRs). The PowerPC general-purpose register file
consists of thirty-two GPRs designated as GPRO-GPR31. The GPRs serve as
data source or destination registers for all integer instructions and provide data
for generating addresses. See "General Purpose Registers (GPRs)," in Chapter 2,
"PowerPC Register Set," of The Programming Environments Manual for more
information.
- Floating-point registers (FPRs). The floating-point register file consists of
thirty-two FPRs designated as FPRO-FPR3 l, which serves as the data source or
destination for all floating-point instructions. These registers can contain data
objects of either single- or double-precision floating-point format For more
information, see "Floating-Point Registers (FPRs)," in Chapter 2, "PowerPC
Register Set," of The Programming Environments Manual.
- Condition register (CR). The CR is a 32-bit register, divided into eight 4-bit
fields, CRO-CR7, that reflects the results of certain arithmetic operations and
provides a mechanism for testing and branching. For more information, see
"Condition Register (CR)," in Chapter 2, "PowerPC Register Set," of The
Programming Environments Manual.
Implementation Note-The PowerPC architecture indicates that in some
implementations the Move to Condition Register Fields (mtcrt) instruction may
perform more slowly when only a portion of the fields are updated as opposed to
all of the fields. The condition register access latency for the 604 is the same in
both cases.
In
the 604, an mtcrf instruction that sets only a single field performs
significantly faster than one that sets either no fields or multiple fields. For more
information regarding the most efficient use of the mtcrf instruction, see
Section 6.6, "Instruction Scheduling Guidelines."
- Floating-point status and control register (FPSCR). The FPSCR contains all
floating-point exception signal bits, exception summary bits, exception enable
bits, and rounding control bits needed for compliance with the IEEE 754
standard For more information, see "Floating-Point Status and Control Register
(FPSCR)," in Chapter 2, "PowerPC Register Set," of The Programming
Environments Manual.
Implementation Note-The PowerPC architecture states that in some
implementations, the Move to FPSCR Fields (mtfst) instruction may perform
more slowly when only a portion of the fields are updated as opposed
to
all of
the fields. In the 604 implementation, there is no degradation of performance.
The remaining user-level registers are SPRs. Note that the PowerPC architecture
provides a separate mechanism for accessing SPRs (the mtspr and mfspr
instructions). These instructions are commonly used to explicitly access certain
PowerPC 604 RISC Microprocessor Uaer'e Manual