IBM PowerPC 604 User Manual page 368

Events selectable for counting by PMCl are listed, along with their MMCR0[19-25]
encodings, in Table 9-2.
Table 9·2. PMC1 Events-MMCRO [19-25] Select Encodings
Encoding
Description
0000000
Nothing. Register counter holds current value.
0000001 Processor cycles are counted
0000010
Count the number of instructions completed per cycle. Legal values are 000, 001, 010, 011, 100.
0000011 RTCSELECT bit transition. (0
=
47, 1
=
51, 2
=
55, 3
=
63)
Bits from the time-base lower register (TBL).
0000100
Number of instructions dispatched. From zero to four instructions per cyde
000 0101 Instruction cache misses (speculative (Instruction cache line-filq)
000 0110 dtlb misses (not speculative)
000 0111 Branch incorrectly predicted
0001000
Number of reservations requested
0001001
Number of
load data
cache misses that exceeded the threshold value with lateral L2 cache
intervention. For more information on L2 cache Intervention, see Section 7.2.10.3, "L2 Intervention
(L2_1Nl)-lnput."
000 1010 Number of store
data
cache misses that exceeded the threshold value with lateral L2 cache
intervention
0001011 Number of mtspr instructions dispatched
0001100 Number of sync instructions completed
000 1101 Number of elelo instructions completed
0001110 Number of integer instructions completed eV8fY cyde (no loads or stores)
000 1111 Number of floating-point Instructions completed every cycle (no loads or stores)
0010000
LSU produced result without an exception condition
001 0001 SCIU1 unit produced result. (add, subtract, compare, rotate, shift, or logical instructions)
001 0010 FPU produced result
001 0011 Number of instructions dispatched to the LSU
001 0100 Number of instructions dispatched to the SCIU1 unit
001 0101
Number Of Instructions dispatched to the floating-point unit
001 0110 Snoop requests received. Valid snoops from outside the 604. Does not know if It is a hit or miss.
001 0111
Number
Of
marked load data cache misses that exceeded the threshold value without lateral L2
intervention.
0011000 Number of marked store
data
cache misses that exceeded the threshold value without lateral L2
intervention
9-4
PowerPC 604 RISC Microprocessor User's Manual