Memory Accesses; Signals - IBM PowerPC 604 User Manual

In addition, the 604 implements a data bus write only signal (DBWO) that can be used for
reordering write operations. Asserting DBWO causes
the
first write operation to occur
before any read operations on a given processor. Although this may be used with any write
operations, it can also be used to reorder a snoop push operation.
Access to the system interface is granted through an external arbitration mechanism that
allows devices to compete for bus mastership. This arbitration mechanism is flexible,
allowing the 604 to be integrated into systems that use various fairness and bus-parking
procedures to avoid arbitration overhead. Additional multiprocessor support is provided
through coherency mechanisms that provide snooping, external control of the on-chip
caches and TLBs, and support for a secondary cache. The PowerPC architecture provides
the load/store with reservation instruction pair (lwarx/stwcx.) for atomic memory
references
and
other operations useful in multiprocessor implementations.
The following sections describe the 604 bus support for memory and direct-store
operations. Note that some signals perform different functions depending upon 'the
addressing protocol used.
1.2.5.1 Memory Accesses
Memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock
cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions.
A single-beat transaction transfers as much as 64 bits. Single-beat transactions are caused
by noncached accesses that access memory directly (that is, reads and writes when caching
is disabled, cache-inhibited accesses,
and
stores in write-through mode). Burst transactions,
which always transfer an entire cache block (32 bytes), are initiated when a block in the
cache is read from or written to memory. Additionally, the 604 supports address-only
transactions used to invalidate entries in other processors' TLBs and caches.
Typically 1/0 accesses are performed using the same protocol as memory accesses. Refer
to Chapter 8, "System Interface Operation," for more information.
1.2.5.2 Signals
The 604 's signals are grouped as follows:
• Address arbitration signals-The 604 uses these signals to arbitrate for address bus
mastership.
• Address transfer start signals-These signals indicate that a bus master has begun a
transaction on the address bus.
• Address transfer signals-These signals, which consist of the address bus, address
parity,
and
address parity error signals, are used to transfer the address and to ensure
the
integrity of the transfer.
• Transfer attribute signals-These signals provide information about the type of
transfer, such as the transfer size and whether the transaction is bursted,
write-through, or cache-inhibited.
1-16 PowerPC 604 RISC Microprocessor
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