Transfer Size (Tsizo-Tsiz2) - IBM PowerPC 604 User Manual

Table 7-1. Transfer Encoding for PowerPC 604 Processor Bus Master (Continued)
TTO TT1 TT2
TT3 TT4
604 Bus Master
Transaction
Transaction Source
Transaction
0 1 0
0
1 TLBSYNC Address only
tlbsync or tlble
0 1 1
0
1 ICBI Address only
NIA
1
x x
0
1 Reserved
-
NIA
0 0 0 1
0
Write-with-flush Single-beat Caching-inhibited or
write or burst write-through store
0 0 1 1 0 Write-with-kill Single-beat Cast-out, or snoop
write or burst copyback
0 1 0 1
0
Read Single-beat Caching-inhibited
read or burst load
0 1
1
1 0 Read-with-Intent- Burst Load miss, or store
to-modify miss
1 0 0 1
0
Write-with-flush- Single-beat stwcx.
atomic write
1
0
1 1
0
Reserved NIA NIA
1 1
0
1
0 Read-atomic Single-beat !wane
read or burst (caching-inhibited
load)
1 1 1
1 0 Read-with-intent- Burst !wane
to-modify-atomic (load miss)
0 0
0
1 1 Reserved
-
NIA
0 0
1
1
1 Reserved
-
NIA
0
1
0
1 1
Read-with-no-
Sing le-beat
NIA
intent-to-cache read or
burst
0
1 1
1
1
Reserved
-
NIA
1
x x
1 1 Reserved
-
NIA
7 .2.4.2 Transfer Size (TSIZO-TSIZ2)
The transfer size (TSIZO-TSIZ2) signals consist of three input/output signals on the 604.
Chapter 7. Signal Descriptions
7-11