IBM PowerPC 604 User Manual page 336

The DRTRY signal is not sampled during data writes, as shown in Figure 8-11.
artiY .
I
AACK I
I
0 2
Figure 8·11. Normal Slngle·Beat Write Termination
3
Normal termination of a burst transfer occurs when TA is asserted for four bus clock cycles,
as shown in Figure 8-12.
The
bus clock cycles in which
TA
is asserted need not be
consecutive, thus allowing pacing of the data transfer beats. For read bursts
to
terminate
successfully,
TEA
and DRlRY must remain negated during the transfer. For write bursts,
TEA must remain negated for a successful transfer. DRTRY is ignored during data writes.
2
3
4 5
6 7
qua/DR
DD
i----\:-+-::o..
I
-..;.--......-------,------...------r--'
drtry I
I
Figure 8-12. Normal Burst Transaction
8-26
PowwPC 604 RISC Micropr0C8980r User's Manual