Powerpc 604 Microprocessor Exceptions - IBM PowerPC 604 User Manual

In many cases, after the exception handler handles an exception, there is an attempt to
execute the instruction that caused the exception. Instruction execution continues until the
next exception condition is encountered. This method of recognizing and handling
exception conditions sequentially guarantees that the machine state is recoverable and
processing can resume without losing instruction results.
To prevent the loss of state information, exception handlers must save
the
information
stored in SRRO and SRRl soon after the exception is taken to prevent this information from
being lost due to another exception being taken.
In this chapter, the following terminology is used to describe the various stages of exception
processing:
Recognition
Taken
Handling
Exception recognition occurs when the condition that can cause an
exception is identified by the processor.
An exception is said to be taken when control of instruction
execution is passed to the exception handler; that is, the context is
saved and
the
instruction at the appropriate vector offset is fetched
and the exception handler routine is begun in supervisor mode.
Exception handling is performed by the software linked to the
appropriate vector offset. Exception handling is begun in supervisor-
level (referred to as privileged state in the architecture specification).
Note that the PowerPC architecture documentation refers to exceptions as interrupts. In this
book, the term interrupt is reserved to refer to asynchronous exceptions, and sometimes to
the event that causes the exception to be taken. Also, the PowerPC architecture uses the
word exception to refer to IEEE-defined floating-point exceptions, conditions that may
cause a program exception to be taken (See Section 4.5. 7, "Program Exception (Ox00700).)
The occurrence of these IEEE exceptions may in fact not cause an exception to
be
taken.
IEEE-defined exceptions are referred to as IEEE floating-point exceptions or floating-point
exceptions.
4.1 PowerPC 604 Microprocessor Exceptions
As specified by the PowerPC architecture, all exceptions can be described as either precise
or imprecise and either synchronous or asynchronous. Asynchronous exceptions are caused
by events external to the processor's execution; synchronous exceptions are caused by
instructions.
The types of exceptions are shown in Table 4.:1. Note that all exceptions except for the
system management interrupt and performance monitoring exception are defined by the
PowerPC architecture.
4-2 PowerPC 604 RISC Microproceeeor User's Manual