Sequential Consistency Within Multiprocessor Systems; Memory And Cache Coherency - IBM PowerPC 604 User Manual

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3.5.3 Sequential Consistency Within Multiprocessor Systems
The PowerPC architecture defines a load operation to have been performed with respect to
all other processors (and mechanisms) when the value to be returned by the load can no
longer be changed by a subsequent store by any processor (or other mechanism). In
addition, it defines a store operation to be performed with respect to all other processors
(and mechanisms) when any load operation from the same location returns the value stored
(or a subsequently stored value).
In
the 604, cacheable load operations and cacheable, non-write-through store operations
are performed with respect to all other processors (and mechanisms) when they have
arbitrated to address the cache. If a cache miss occurs, these operations may drop a memory
request into the processor's memory queue, which is considered an extension to the state
of the cache with respect to snooping bus operations.
However, cache-inhibited load operations and cache-inhibited or write-through store
operations are performed with respect to other processors (and mechanisms) when they
have been successfully presented onto the 604 bus interface. As a result, if multiple
processors are performing these types of memory operations to the same addresses without
properly synchronizing one another (through the use of the lwarx/stwcx. instructions), the
results of these instructions are sensitive to the race conditions associated with the order in
which the processors are granted bus access.
If the 604 uses an L2 cache, the system designer must ensure the memory system responds
to the SYNC and EIEIO bus operations in such a way that the required ordering of memory
operations is preserved.
3.6 Memory and Cache Coherency
The 604 can support a fully coherent 4-Gbyte (2
32 )
memory address space. Bus snooping
is used to drive a four-state (MESI) cache coherency protocol which ensures the coherency
of
all
processor and direct-memory access (DMA) transactions to and from global memory
with respect to each processor's cache. It is important that all bus participants employ
similar snooping and coherency control mechanisms. The coherency of memory is
maintained at a granularity of 32-byte cache blocks (this size is also called the coherency
or cache-block size).
All instruction and data accesses are performed under the control of the four memory/cache
access attributes:
Write-through (W attribute)
Caching-inhibited (I attribute)
Memory coherency (M attribute)
Guarded (G attribute)
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PowerPC 604 RISC Microprocessor User's Manual

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