IBM PowerPC 604 User Manual page 36

- Four-entry finish load queue
(FLQ)
provides load miss buffering
- Six-entry store queue
- Supports both big- and little-endian modes
• Rename buffers
- Twelve GPR rename buffers
- Eight FPR rename buffers
- Eight condition register (CR) rename buffers
The 604 rename buffers are described in Section 1.2.1.5, "Rename Buffers."
• Completion unit
- Retires an instruction from the 16-entry reorder buffer when all instructions
ahead of it have been completed and the instruction has finished execution
- Guarantees sequential programming model (precise exception model)
- Monitors all dispatched instructions and retires them in order
- Tracks unresolved branches and removes speculatively executed, dispatched,
and fetched instructions if branch is mispredicted
- Retires as many as four instructions per clock
• Separate on-chip instruction and data caches (Harvard architecture)
- 16-Kbyte, four-way set-associative instruction and data caches
- LRU replacement algorithm
- 32-byte (eight word) cache block size
- Physically indexed; physical tags. Note that the PowerPC architecture refers to
physical address space as real address space.
- Cache write-back or write-through operation programmable on a per page or per
block basis
- Instruction cache can provide four instructions per clock cycle; data cache can
provide two words per clock cycle.
- Caches can be disabled in software
- Caches can be locked
- Parity checking performed on both caches
- Data cache coherency (MESI) maintained in hardware
- Secondary data cache support provided
- Instruction cache coherency maintained in software
- Provides a no-DRTRY/data streaming mode, which allows consecutive burst
read data transfers to occur without intervening dead cycles. This mode also
disables
data
retry operations.
• Separate memory management units (MMUs) for instructions and data
Chapter 1.
Overview 1-5