Serialization Of String/Multiple Instructions; Serialization Of Input/Output; Execution Unit Timings; Branch Unit Instruction Timings - IBM PowerPC 604 User Manual

6.4.7.4 Serialization of String/Multiple Instructions
Serialization is required for all load/store multiple/string instructions. These instructions
are broken into a sequence of register-aligned operations. The first operation is dispatched
along with any preceding instructions in the dispatch buff er. Subsequent operations are
dispatched one-word-per-cycle until the operation is finished. String/multiple instructions
remain in the dispatch buffer for at least two cycles even if they only require a single-word-
aligned memory operation.
Instructions causing string/multiple serialization include lmw, stmw, lswi, lswx, stswi, and
stswx. ,
6.4. 7 .5 Serialization of Input/Output
In this serializationmode, all noncacheable loads are performed in order with respect to the
eieio instruction.
6.5 Execution Unit Timings
The following sections describe instruction timing considerations within each of the
respective execution units in the 604. Refer to Table 6-2 for branch instruction execution
timing.
6.5.1 Branch Unit Instruction Timings
The 604 can have two unresolved branches in the branch reservation station and two
resolved branches that have not yet completed. The branch unit serves to validate branch
predictions made in earlier stages. It also verifies that the predicted target matches the
actual target address.
If
a misprediction is detected, it redirects the fetch to the correct
address and starts the branch misprediction recovery.
The branch execution unit also executes condition register logical instructions, which the
PowerPC architecture provides for calculating complex branch conditions. Other
architectures that lack such instructions would need to use a series of branch instructions to
resolve complex branching conditions. All execution units can update the CR fields, but
only the branch and CR logical operations use CR fields as source operands.
6.5.2 Integer Unit Instruction Timings
The two SCIUs and the MCIU execute all integer and bit-field instructions, and are shown
in Figure 6-14 and Figure 6-15, respectively.
The SCIUs consist of three one-cycle subunits:
• A fast adder/comparator subunit
• A logic subunit
• A rotator/shifter/count-leading zero subunit
Chapter &. Instruction Timing
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