IBM PowerPC 604 User Manual page 433

-
Cache coherency
cache coherency protocol. 3-11
cache snoop, 3-19
coherency paradoxes, 3-14, 3-15
L2 cache, 3-13
MESI
protocol, 3-14
reaction to bus operations, 3-19
Cache control instructions
bus operations, 3-23
dcbf, 3-18
dcbi, 2-54, 3-18
dcbst, 3-17
debt,
2-51, 3-17
dcbtst, 3-17
dcbz, 3-17
icbi, 3-16
isync, 3-17
Cache hit
instruction timing example, 6-19
Cache implementation, 604, 1-12
Cache management instructions, A-26
Cache miss, 6-22
Cache operations
overview, 3-1
response to bus transactions, 3-19
types of operations, 3-18
Cache reload operation, 3-18
Cache unit
operation of the cache, 8-2
Cache-inhibited accesses (I-bit)
memory/cache access attributes, 3-10
performance considerations, 6-16
Changed
(C)
bit maintenance
recording, 5-12, 5-21-5-22
updates, 5-33
Checkstop signal, 7-26, 8-51
Checkstop state, 4-15
CI
signal, 7-14
Classes of instructions, 2-21
Clean block operation, 3-20
Cloclc signals
CLK_OUT, 7-31
PLL_CFGO-PLL_CFG3, 7-31
SYSCLK, 7-30
Completion
completion considerations, 6-30
completion pipeline stage, 6-11
completion unit, 1-9
definition, 6-3
Context synchronization, 2-24
COP/scan interface, 7-29
lndex-2
INDEX
CR (condition register)
CR logical instructions, 2-45
CR,
description, 2-4
CS~El
signals, 7-15, 8-30
CIR register, 2-5
D
DABR (data address breakpoint register), 2-7
DAR (data address register), 2-6
Data bus
arbitration signals
DBB, 7-19, 8-8
DBG, 7-18, 8-8
DBWO, 7-18, 8-8
bus arbitration
ARlRY assertion, effect of, 8-21
signals, 8-20
data
tenure, 8-7, 8-39
data
transfer
alignment, 8-14
ARTRY
assertion, effect of, 8-21
bunt ordering, 8-14
DBDIS, 7-22
DHO-DH31/DLO-DL31, 7-20, 8-23
DPO-DP7, 7-21, 8-23
DPE, 7-22, 8-23
eciwx/ecowx instructions, alignment, 8-16
data transfer termination
DRlRY, 7-23, 8-24
enortennination, 8-28
TA, 7-23, 8-24
TEA, 7-24, 8-24
terminating data transfer, 8-24
Data cache
data caches and memory queues, 6-14
disabling and enabling, 3-3
organization, 3-3
Data organization in memory, 2-17
mm
signal, 7-19, 8-8, 8-22
DBDIS signal, 7-22
DBG signal, 7-18, 8-8
'DBWO
signal, 7-18, 8-8, 8-23, 8-53
dcbt,2-51
DEC (decrementer register), 2-7
Decode stage, 6-9
Decode/dispatch 1mit, 1-9
Decrementer exception, 4-19
Defined instruction class, 2-21
DHO-DH31/DLO-DL31 signals, 7-20
PowerPC 604 RISC Microproceasor User's Manuel