IBM PowerPC 604 User Manual page 355

Address Bus (AO-A31)
0 7 0 123
1112 27 28 31
. . . . I
--~--:r--c---.1
+
l/OOpcode
r
~ , . R - e g - i s _ t e _ r
_ _ _ _ _ _
PIO
Reserved
Figure 8-25. 1/0 Reply Operation
The address bits are described in Table 8-9.
Table 8-9. Address Bits for 110 Reply Operations
Address Bits Description
0-1 Reserved.
These bits
should be deared for compatbiUty with future PowerPC microprocessors.
2 Error bit. It is set H the BUC records
an
error in the
access.
3-11 BUIO. Sender tag of a reply operation. Corresponds with bits 3-11 of one of the 604 segment
registers.
12-27 Address
bits
12-27
are
BUC-speciflc and are ignored by the 604.
28-31 PIO (receiver tag).
The
604 effectively snoops operations on the bus and, on reply operations,
compares this field
to bits
28-31 of the PIO register to determine H It should recognize this VO reply.
The second beat of the address bus is reserved; the XATC
and
address buses should be
driven to zero to preserve compatibility with future protocol enhancements.
The following sequence occurs when the 604 detects an error bit set on an 1/0 reply
operation:
1. The 604 completes the instruction that initiated the access.
2.
If
the instruction is a load, the data is forwarded onto the register file(s)/sequencer.
3. A direct-store error exception is generated, which transfers 604 control to
the
direct-
store error exception handler to recover from the error.
If
the error bit is not set, the 604 instruction that initiated the access completes
and
instruction execution resumes.
Chapter 8. System Interface
Operation
8-45