IBM PowerPC 604 User Manual page 57

The 604 supports all IEEE 754-1985 floating-point data types (normalized,
denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred
by software exception routines.
The Power PC architecture also supports a non-IEEE mode, controlled by a bit in the
FPSCR. In this mode, denonnalized numbers, NaNs, and some IEEE invalid
operations are not required to conform to IEEE standards and can execute faster.
Note that all single-precision arithmetic instructions are performed using a
double-precision format. The floating-point pipeline is a single-pass implementation
for double-precision products. For almost all floating-point instructions, a
single-precision instruction using only single-precision operands in
double-precision format performs the same as its double-precision equivalent.
• Load/store instructions-These include integer and floating-point load and store
instructions.
- Integer load and store instructions
- Integer load and store multiple instructions
- Integer load and store string instructions
- Floating-point load and store
• Flow control instructions-These include branching instructions, condition register
logical instructions, trap instructions, and other instructions that affect the
instruction flow.
- Branch and trap instructions
- System call and rfi instructions
- Condition register logical instructions
• Synchronization instructions-The PowerPC architecture defines instructions for
memory synchronizing, especially useful for multiprocessing:
- Load and store with reservation instructions-These UISA-defined instructions
provide primitives for synchronization operations such as test and set, compare
and swap, and compare memory.
- The Synchronize instruction (sync)-This UISA-defined instruction is useful for
synchronizing load and store operations on a memory bus that is shared by
multiple devices.
- The Instruction Synchronize instruction (isync)-This instruction causes the
604 to purge its instruction buffers and fetch the double word containing the next
sequential instruction.
- The Enforce In-Order Execution of 1/0 instruction ( eieio )-The eieio
instruction, defined by the VEA, can be used instead of the sync instruction when
only memory references seen by 1/0 devices need to be ordered.
• Processor control instructions-These instructions are used for synchronizing
memory accesses and managing caches, TLBs, and segment registers. These
instructions include move to/from special-purpose register instructions (mtspr and
mfspr).
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PowerPC 604 RISC Microprocessor User's Manual