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Figure 8-27. Direct-Store Interface Store Access Example
8. 7 Optional Bus Configuration
The 604 supports an optional bus configuration that is selected by the assertion or negation
of the DRTRY signal during the negation of the HRESET signal. The operation and
selection of the optional bus configuration is described in the following section.
8. 7 .1 Fast·L2/Data Streaming Mode
The 604 supports an optional mode (described as the fast-L2/data stteaming mode}, that
disables the use of the data retry function provided through the DRTRY signal. Although
this bus interface mode implies its suitability for use in interfacing to a second-level cache,
the fast-L2/data streaming mode allows the forwarding of data during load operations to
the internal CPU one bus cycle sooner than in the normal bus protocol. The PowerPC bus
protocol specifies that, during load operations, the memory system normally has the
capability to cancel data that was read by the master on the bus cycle
afu;..
TA was asserted.
In the 604 implementation, this late cancellation protocol requires the 604
to hold any
loaded data at the bus interface for one additional bus clock to verify that the data is valid
before forwarding it to the internal CPU. The use of the optional fast-L2/data streaming
mode eliminates the one-cycle stall during all load operations, and allows for the
forwarding of data to the internal CPU immediately when TA is recognized, thereby
increasing maximum read bandwidth.
When the 604 is following normal bus protocol, data may be cancelled the bus cycle after
TA by either of two means-late cancellation by DRTRY, or late cancellation by ARTRY.
When the fast-L2/data streaming mode is selected, both cancellation cases must be
disallowed in the system design for the bus protocol.
8-48
PowerPC 604 RISC Microproceeeor User's Manual
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