Cache Arbitration; Branch Prediction - IBM PowerPC 604 User Manual

6.4.3 Cache Arbitration
When a cache miss occurs, a line-fill operation is initiated
to
update the appropriate cache
block. When the double word containing the data at the specified address (the critical
double word) is available, it is forwarded to the cache and made available
to
other resources
on the 604. Likewise, subsequent double words are also forwarded as they reach the
memory
unit.
Fetches
to
different lines can hit in the cache during the line-fill operation; however, if a
miss occurs before the cache block has been updated, the line-fill operation must complete
before the line-fill operation caused by the subsequent miss can begin.
For more information about the cache implementation in the 604, see Chapter 3, "Cache
and Bus Interface Unit Operation."
6.4.4 Branch Prediction
The 604 implements several features
to
reduce the latencies caused by handling branch
instructions. In particular, it provides a means of dynamic branch prediction. This is
especially critical for the 604
to
take fullest advantage of the possibilities of increased
throughput made available from its pipelined and highly parallel organization. Dynamic
branch prediction is implemented in the fetch, decode, and dispatch stages, as described in
the following: ·
In the fetch stage, the fetch address is used to access the branch target address cache
(BTAC), which contains the target address of previously executed branch instructions that
are predicted
to
be taken. The 64-entry BTAC is fully associative
to
provide a high hit
percentage. If a fetch address is in the BTAC, the target address is used in the next cycle
to
fetch the instructions from the predicted path. If the address is not present, sequential
instruction flow is assumed and the appropriate sequential address is generated based on
the number of instructions added
to
the decode buffer. The fetch address, rather than the
first branch address, is sufficient
to
access the BTAC, since a BTAC entry contains the first
predicted taken branch beyond the current fetch address.
In the decode and dispatch stages, the first branch instruction is identified and its outcome
is predicted. For an unconditional branch instruction, the instruction prefetch is redirected
to
the target address if this branch was predicted as not taken by a previous stage.
Conditional instructions whose direction depends on the value in the CIR are predicted
based on that value. If the prediction differs from the current branch prediction, the prefetch
is redirected.
For conditional branch instructions that depend only on a bit in the CR, the BHT is used for
the prediction. The BHT is a 512-entry, direct-mapped cache with 2 bits .that can indicate
four prediction states-strongly taken, taken, not-taken, and strongly not-taken. The entry
is updated each time a conditional branch instruction that depends on a bit in the condition
register is executed. For example, a BHT entry that predicts "taken" is updated
to
"strongly
taken" after the branch is taken or is updated
to
"not-taken" if the next branch is not-taken.
6-24 PowerPC 604 RISC Microproceuor User's Manual