Isync, Rfi, And Sc Instruction Timings - IBM PowerPC 604 User Manual

Figure 6-18 shows the structure of the store queue. There are four regions that identify the
state of the store instructions.
Empty
Figure 6-18. Store Queue Structure
When a store instruction finishes execution, it is placed in the finished state. When it is
completed, the finish pointer advances to place it in the completed state. When the store
data is committed to memory, the completion pointer advances to place it in the committed
state. If the store operation hits in the cache, the commit pointer advances to effectively
remove the instruction from the queue. Otherwise, the commit pointer does not advance
until the cache block is reloaded and the store operation can occur. During this time, the
next store instruction pointed to by the completion pointer can access the cache. If this
second store instruction hits in the cache, it is removed from the queue. If not, another cache
block reload begins.
6.5.5 isync, rfi, and sc Instruction Timings
The isync, rfi, and sc instructions do not execute in one of the execution units. These
instructions decode to branch unit instructions, as specified by the PowerPC architecture,
but they do not actually execute in the BPU in the same sense that other branch instructions
do. The completion unit treats the rfi and sc instructions as exceptions, and handles them
precisely. When an isync instruction reaches the top of the completion buffer, subsequent
instructions are flushed from the pipeline and are refetched during the next clock cycle.
Although the rfi and sc are dispatched to the branch reservation stations, these instructions
do not execute in the ordinary sense, and do not occupy a position in an execute stage in
one of the BPU. Instead, these instructions are given a position in the completion buffer at
dispatch. When the sc instruction reaches the top of the completion buffer, the system call
exception is taken. When the rfi instruction reaches the top of the completion buffer, the
necessary operations required for restoring the machine state upon returning from an
exception are performed.
The isync instruction causes instructions to be flushed when it is completed. This means
that the decode buffers, dispatch buffers, and execution pipeline are all flushed Fetching
resumes from the instruction following the isync.
Chapter 6. Instruction Timing
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