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The 604 fully decodes the SPR field of the instruction. If an undefined SPR is specified, a
program exception is taken.
The UISA defines the mtspr and mfspr instructions with the record bit (Re) set to cause a
program exception or provide a boundedly undefined result. In the 604, the appropriate CR
should be treated as undefined. Likewise, the PowerPC architecture states that the Floating
Compared Unordered (fcmpu) or Floating Compared Ordered (fcmpo) instruction with the
record bit set can either cause a program exception or provide a boundedly undefined result.
In the 604, CR field BF for these cases should be treated as undefined.
When a program exception is taken, instruction execution resumes at offset Ox00700 from
the physical base address indicated by MSR[IP].
Note that the 604 supports one of the two floating-point imprecise modes supported by the
PowerPC architecture. The three modes supported by the 604 are described as follows:
•
Ignore exceptions mode (MSR[FEO]
=
MSR[FEl]
=
0)-In ignore exceptions
mode, the instruction dispatch logic feeds the FPU as fast as possible, and the FPU
uses an internal pipeline to allow overlapped execution of instructions. IEEE
floating-point exception conditions (as defined in the PowerPC architecture) do not
cause any exceptions.
•
Precise exceptions mode (MSR[FEO]
=
1; MSR[FEl]
=
x)-In this mode, a floating
point instruction that causes a floating-point exception brings the machine to a
precise state. In doing so, the 604 sequencer unit can detect floating-point exception
conditions and take floating-point exceptions as defined by the PowerPC
architecture. Note that the imprecise recoverable mode supported by the PowerPC
architecture (MSR[FEO]
=
1; MSR[FEl]
=
0) is implemented identically to precise
exceptions mode in the 604.
•
Imprecise nonrecoverable mode (MSR[FEO]
=
0; MSR[FE 1]
=
1 )-In this mode,
floating-point exception conditions cause a floating-point exception to be taken,
SRRO may point to some instruction following the instruction that caused the
exception.
Register settings for this exception are described in Chapter 6, "Exceptions," in The
Programming Environments Manual.
4.5.8 Floating-Point Unavailable Exception (Ox00800)
The floating-point unavailable exception is implemented as defined in the PowerPC
architecture.
A
floating-point unavailable exception occurs when no higher priority
exception exists, an attempt is made to execute a floating-point instruction (including
floating-point load, store, or move instructions), and the floating-point available bit in the
MSR is disabled, (MSR[FP]
=
0). Register settings for this exception are described in
Chapter 6, "Exceptions," in
The Programming Environments Manual.
When a floating-point unavailable exception is taken, instruction execution resumes at
offset Ox00800 from the physical base address indicated by MSR[IP].
4·18
PowerPC 604 RISC Microprocessor User's Manual
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