Machine Check Exception Enabled (Msr[Me] 1) - IBM PowerPC 604 User Manual

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Machine check conditions can be enabled and disabled using bits in the HIDO described in
Table4-7.
Table 4-7. Machine Check Enable Bits
HIDO Bit Description
0
Enable machine check input pin
1 Enable cache parity checking
2 Enable machine check on address bus parity error.
3 Enable machine check on data bus
parity
error.
A TEA indication on the bus can result from any load or store operation initiated by the
processor. In general, the TEA signal is expected
to
be used by a memory controller to
indicate that a memory parity error or an uncorrectable memory ECC error has occurred.
Note that the resulting machine check exception is imprecise and unordered with respect to
the instruction that originated the bus operation.
If the MSR[ME] bit and the appropriate bits in HIDO are set, the exception is recognized
and handled; otherwise, the processor generates an internal checkstop condition. When a
processor is in checkstop state, instruction processing is suspended and generally cannot
continue without restarting the processor. Note that many conditions may lead to the
checkstop condition; the disabled machine check exception is only one of these.
Machine check exceptions are enabled when MSR[ME]
=
1; this is described in
Section 4.5.2.1, "Machine Check Exception Enabled (MSR[ME] = 1)." If MSR[ME] = 0
and a machine check occurs, the processor enters the checkstop state. Checkstop state is
described in Section 4.5.2.2, "Checkstop State (MSR[ME]
=
O)."
4.5.2.1 Machine Check Exception Enabled (MSR[ME]
=
1)
When a machine check exception is taken, registers are updated as shown in Table 4-8.
4-14
PowerPC 604 RISC Microprocessor User's Manual