Transfer Code (Tco-Tc2) Signals - IBM PowerPC 604 User Manual

between the two transfers. Also, the two bus operations associated with a misaligned ecowx
may be interrupted by an eciwx bus operation, and vice versa. The 604 does guarantee that
the two operations associated with a misaligned ecowx will not be interrupted by another
ecowx operation; and likewise for eciwx.
Because a misaligned external control address is considered a programming error, the
system may choose some means
to
cause an exception, typically by asserting
TEA
to
cause
a machine check exception or INT to cause an external interrupt, when a misaligned
external control bus operation occurs.
8.3.2.5 Transfer Code (TCO-TC2) Signals
The TCO-TC2 signals provide supplemental information about the corresponding address.
Note that the TCx signals can be used with the WT, TTO-TI4 and TBST signals
to
further
define the current transaction. When asserted, the transfer codes have the following
meanings:
• TCO
- Read cycle: indicates code fetch
- Write cycle: de-allocation from Ll cache
• TCl
- Write cycle: indicates new cache state is shared
• TC2
- Read and write cycle: indicates allocation cycle utilized a copy-back buffer
Table 8-6 shows the supplemental information provided by the TCO-TC2 and WT signals.
Table 8-6. Transfer Code Encoding
TT Type Code
WT'
TCO TC1 TC2 Operation
Write with kill
1 1 0
0 Cache copyback
Write with kill
0 1 0
0
Block Invalidate
(debt)
Write with kill 0 0 0 0 Block clean
(clcbst)
Write
with
kill
0
0 1 0 Snoop push
(read operation)
Write with kill
0 1
0 0 Snoop push
(read-with-intent-to-modHy)
Write with kill
0 0
0 0 Snoop push
(clean operation)
Write with kill
0
1 0 0 Snoop push
(flush operation)
KiHblock x
1 0
0
KiU block de-allocate
(dcbl)
Chapter 8. Sy•tem Interface Operation 8-17