IBM PowerPC 604 User Manual page 194

hi addition to the higher-order address bits, the MMUs automatically keep an indicator of
whether each access was generated as an instruction or data access and a supervisor/user
indicator that reflects the state of the PR bit of the MSR when the effective address was
generated. In addition, for data accesses, there is an indicator of whether the access is for a
load or a store operation. This infonnation is then used by the MMUs to appropriately direct
the address translation and to enforce the protection hierarchy programmed by the
operating system. Section 4.3, "Exception Processing," describes the MSR, which controls
some of the critical functionality of the MMUs.
The figures show the way in which the A20-A26 address bits index into the on-chip
instruction and data caches to select a cache set. The remaining physical address bits are
then compared with the tag fields (comprised of bits PAO-PAl 9) of the two selected cache
blocks to determine if a cache hit has occurred. In the case of a cache miss, the instruction
or data access is then forwarded to the bus interface unit which then initiates an external
memory access.
Chapter 5. Memory Management
5-5