Cache Control Instructions; Cache Actions - IBM PowerPC 604 User Manual

3.9.9 Cache Control Instructions
Table 3-5 lists bus operations performed by the 604 when they execute cache control
instructions.
Table 3-5. 604 Bus Operations Initiated by cache Control Instructions
Instruction Cache State Next Cache State Bus Operation
Comment
sync Donicare No change SYNC First clears memory queue
elelo Don't care No change
EIEIO
No clear meaning
lcbl Don't care I ICBI
-
dcbl Don't care I
Kill
-
(invalidate)
dcbf E,S,I I Flush
-
(flush)
M I Write-with-kill Marked as write-through
dcbst
E,S,I No change
Clean
-
(store)
M E Write-with-kill Marked as write-through
dcbz
I M
Kill
May also replace
(zero)
s
M
KHI
-
M,E M
None
Write over modified data
debt, dcbtst
I
E,S Read State change on reload
M,E,S No Change None
-
tlbsync Don't care
No change
TLBSYNC
-
Table 3-5 does not include noncacheable or write-through cases, nor does it completely
describe the mechanisms for the operations described. For more information, see
Section 3.10, "Cache Actions."
Chapter 3, "Addressing Modes and Instruction Set Summary," and Chapter 8, "Instruction
Set," in
The Programming Environments Manual
describe
th~
cache control instructions in
detail. Several of the cache control instructions broadcast onto the 604 interface so that
all
processors in a multiprocessor system can take appropriate actions. The 604 contains
snooping logic to monitor the bus for these commands and the control logic required to
keep the cache and the memory queues coherent. For additional details about the specific
bus operations performed by the 604, see Chapter 8, "System Interface Operation."
3.1 O Cache Actions
Table 3-6 lists the actions that occur for various operations depending on different WIM bit
settings.
Chapter 3. Cache and Bus Interface Unit Operation
3-23