Memory Access Protocol - IBM PowerPC 604 User Manual

address transfer start signals-TS indicates that a memory transfer is starting and XATS
indicates that a direct-store transaction is starting.
Direct-store accesses are strongly ordered-each access occurs in strict program order and
completes before another access can begin. For this reason, direct-store accesses are less
efficient than memory accesses. The direct-store extensions also allow for additional bus
pacing
and
multiple transaction operations for variably-sized data transfers (1 to 128 bytes),
and they support a tagged, split request/response protocol. The direct-store access protocol
also requires the slave device to function as a bus master.
8.2 Memory Access Protocol
Memory accesses are divided into address and data tenures. Each tenure has three phases-
bus arbitration, transfer, and termination. The 604 also supports address-only transactions.
Note that address and data tenures can overlap, as shown in Figure 8-3.
Figure 8-3 shows that the address and data tenures are distinct from one another and that
both consist of three phases-arbitration, transfer, and tennination. Address and data
tenures are independent (indicated in Figure 8-3 by the fact that the data tenure begins
before the address tenure ends), which allows split-bus transactions to be implemented at
the system level in multiprocessor systems. Figure 8-3 shows a data transfer that consists
of a single-beat transfer of as many as 64 bits. Four-beat burst transfers of 32-byte cache
lines require data transfer termination signals for each beat of data.
ADDRESS TENURE
ARBITRATION TRANSFER TERMINATION
INDEPENDENT ADDRESS AND DATA
\ DATA TENURE
--~~~~~~~--
I
ARBITRATION
I
SINGLE-BEAT TRANSFER
I
TERMINATION
I
Figure 8-3. Overlapping Tenures on the PowerPC 604 Microprocessor Bus for a
Single-Beat Transfer
The basic functions of the address and data tenures are as follows:
8-6
• Address tenure
- Arbitration: During arbitration, address bus arbitration signals are used to gain
mastership of the address bus.
- Transfer: After the 604 is the address bus master, it transfers the address on the
PowerPC 604 RISC Microprocessor User's Manual