Effect Of Operand Placement On Performance; Instruction Set Summary - IBM PowerPC 604 User Manual

Table 2-8 summarizes the mode behavior for results.
Table 2-8. Floating-Point Result Data Type Behavior
Precision Data Type IEEE Mode (NI : 0)
Non-IEEE Mode (NI= 1)
Single
Denormalized Return single-precision Return zero.
denormalized number with trailing
zeros.
Single Normalized Return the result.
Return the result.
Infinity
Zero
Single QNaN
ReturnONaN. ReturnONaN.
SNaN
Single INT Place integer into low word of FPR. H (Invalid Operation)
then
Place (Ox8000) into FPR(32-63)
else
Place integer into FPR(32-63].
Dolble Denormalized Return double precision Return zero.
denormalized number.
Dolble Normalized Return the result. Return the result.
Infinity
Zero
Dolble ONaN
ReturnONaN.
ReturnONaN.
SNaN
Do Ible INT Not supported by 604 Not supported by 604
2.2.5 Effect of Operand Placement on Performance
The PowerPC VEA states that the placement (location and alignment) of operands in
memory may affect the relative performance of memory accesses. The best performance is
guaranteed if memory operands are aligned on natural boundaries. To obtain the best
performance across the widest range of PowerPC processor implementations, the
programmer should assume the performance model described in Chapter 3, "Operand
Conventions," in
The Programming Environments Manual.
2.3 Instruction Set Summary
This chapter describes instructions and addressing modes defined for the 604. These
instructions are divided into the following functional categories:
• Integer instructions-These include arithmetic and logical instructions. For more
information, see Section 2.3.4.1, "Integer Instructions."
• Floating-point instructions-These include floating-point arithmetic instructions, as
well as instructions that affect the floating-point status and control register (FPSCR).
For more information, see Section 2.3.4.2, "Floating-Point Instructions."
Chapter 2. PowerPC 604 Proceeeor Programming Model
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