Self-Modifying Code - IBM PowerPC 604 User Manual

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• Any operation that crosses a word boundary (double word for floating-point doubles
aligned on a double-word boundary) is broken into two accesses. Each of these
accesses is translated.
If either translation results in a data memory violation, a DSI
exception is signaled.
If two translations cross from T
=
1 into T
=
0 space (a
programming error), the 604 completes all of the accesses for the operation, the
segment information from the T
=
1 space is presented on the bus for every access
of the operation, and he 604 requires a direct-store protocol "Reply" from the
device.
If two translations cross from T
=
0 into T
=
1 space, a DSI exception is
signaled.
• In
the PowerPC architecture, the Re bit must be zero for almost all load and store
instructions.
If the Re bit is one, the instruction form is invalid. These include the
integer load indexed instructions (lbzx, lbzux, lhzx, lhzux, lhax, lhaux, lwzx,
lwzux), the integer store indexed instructions (stbx, stbux, sthx, sthux, stwx,
stwux), the load and store with byte-reversal instructions (lhbrx, lwbrx, sthbrx,
stwbrx), the string instructions (lswi, lswx, stswi, stswx), and the synchronization
instructions (sync, lwarx). In the 604, executing one of these invalid instruction
forms causes CRO to be set to an undefined value. The floating-point load and store
indexed instructions (lfsx, lfsux, lfdx, lfdux, stfsx, stfsux, stfdx, stfdux) are also
invalid when the Re bit is one.
In
the 604, executing one of these invalid instruction
forms causes CRO to be set to an undefined value.
2.3.4.3.1 Self-Modifying Code
When a processor modifies a memory location that may
be
contained in the instruction
cache, software must ensure that memory updates are visible to the instruction fetching
mechanism. This can
be
achieved by the following instruction sequence:
dcbst lupdate memoiy
sync lwait for update
lcbl I remove (invalidate) copy in instruction cache
sync lwait for icbi
to
be globally perfonned
lsync lremove copy in o'Wn instruction buffer
These operations are required because the data cache is a write-back cache. Since
instruction fetching bypasses the data cache, changes to items in the data cache may not be
reflected in memory until the fetch operations complete.
Special care must be taken to avoid coherency paradoxes in systems that implement unified
secondary caches, and designers should carefully follow the guidelines for maintaining
cache coherency that are provided in the VEA, and discussed in Chapter 5, "Cache Model
and Memory Coherency," in
The Programming Environments Manual. Because the 604
does not broadcast the M bit for instruction fetches, external caches are subject to
coherency paradoxes.
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PowerPC 604 RISC Microprocessor User's Manual