Packet 0; 1/0 Reply Operations - IBM PowerPC 604 User Manual

8.6.2.2 Packet 1
The second address beat, packet 1, transfers byte counts and the physical address for the
transaction, as shown
in
Figure 8-24.
ADDA +
--{P,K'.Jtt(PKT 1)
0 7 0 3 4 31
I XATC I
+
..-~-R(-28-3-
..... 1j _ _ _ _ _ _ _ _
Bu_s_A_d_d~-e-ss-----------.I
Byte Count Address Bus (AO-A31)
Figure 8-24. Direct-Store Operation-Packet 1
For packet 1, the XATC is defined as follows:
• Load request operations-XATC contains the total number of bytes to be transferred
(128 bytes maximum for 604).
• Immediate/last (load or store) operations-XATC contains the current transfer byte
count (1 to 4 bytes).
Address bits
0-31
contain the physical address of the transaction. The physical address is
generated by concatenating segment register bits 28-31 with bits 4-31 of the effective
address, as follows:
Segment register (bits
28-31)
II effective address (bits
4-31)
While the 604 provides the address of the transaction to the BUC, the BUC must maintain
a valid address pointer for the reply.
8.6.3 1/0 Reply Operations
BUCs must respond
to
604 direct-store transactions with an 1/0 reply operation, as shown
in Figure
8-25.
The purpose of this reply operation is to inform the 604 of the success or
failure of the attempted direct-store access. This requires the system direct-store
to
have
604 bus mastership capability-a substantially more complex design task than bus slave
implementations that use memory-mapped 1/0 access.
Reply operations from the BUC to the 604 are address-only transactions. As with packet 0
of the address bus on 604 direct-store operations, the XATC contains the opcode for the
operation (see Table 8-8). Additionally, the 1/0 reply operation transfers the sender/receiver
tags in the first beat.
8-44
PowerPC 604 RISC Microprocessor User's Manual