IBM PowerPC 604 User Manual page 270

multiple/string operations, monopolize these internal hardware resources, which can
affect performance. For software portability, such instructions should
be
avoided,
even though they
do
not suffer the performance degradation in the 604 that they
might in other PowerPC processors. The most common use of such instructions is
in subroutine prologues or epilogues The following alternatives are typically more
efficient:
- Expanding the register save/restore code in-line
- Branching to special save/restore functions (sometimes called millicode) that use
in-line sequences of save and restore instructions.
• Use the load with update instruction judiciously.
Another frequently used set of instructions that are subject to this multiple register
usage effect are the load with update instructions. While use of such instructions is
usually desirable from a performance standpoint (they eliminate a dependent integer
operation), care must still be taken to not issue too many of these instructions
consecutively.
• Schedule code to take advantage of rename registers.
As discussed previously, the 604 provides register renaming as a means of
improving execution
speed.
Since there are a limited number of rename buffers
implemented in hardware, it is always desirable to minimize pressure on this
resource. One relatively simple means of doing this is to use immediate addressing
when the option exists. For example, an integer register copy can be performed in a
single cycle using a number of different instructions. However, using an ori
instruction (with an immediate operand of zero) uses only one source register
operand; whereas, the register indirect form of the or instruction uses two source
registers.
• Minimi7.e use of instructions that serialize execution.
Some operations, such as memory synchronization primitives
and
trap instructions,
have well-known serialization properties that are intended when used by a
programmer. Other instructions, however, have more subtle serialization effects that
may affect performance. For example, if operations that manipulate condition
register fields are used frequently, they can significantly hinder performance,
particularly when multiple condition fields are being accessed by a single
instruction, described in the following:
• Avoid using the mtcrf instruction
to
update multiple fields.
6·44
Note that the performance of the mtcrf instruction depends greatly on whether only
one field is accessed or either no fields or multiple fields are accessed as follows:
- Those mtcrf instructions that-update only one field are executed in either of the
SCIUs and the CR field is renamed as with any other SCIU instruction.
- Those mtcrf instructions that update either multiple fields or no fields are
dispatched to the MCIU and a count/link scoreboard bit is seL When that bit is
set, no more mtcrf instructions of the same
type,
mtspr instructions that update
PowerPC 604 RISC Microprocessor User's Manual