IBM PowerPC 604 User Manual page 440

INDEX
TIB
description, 5-24
LRU replacement, 5-26
organization for l1LB and DTI..B 5-24
TIB miss and table search operatlon, 5-25 5-29
~2
• .
TIB invalidation
description, 5-19, 5-26
page table updates, 5-33
TIB invalidate and TIBSYNC operations, 3-21,
5-26, 5-27, 7-10
TIB invalidate broadcast operations, 5-26
11..B management instructions, A-27
tibia (not implemented), 2-56, 5-27
tlbie, 2-55, 2-56, 5-26, 5-33
tlbsync, 2-55, 2-56, 5-27, 5-34
tlbie, 2-56, 5-26, 5-33
tlbsync, 2-56, 5-27, 5-34
Trace exception, 4-19
Transfer, 8-12, 8-23
Trap instructions, 2-45
TS signal, 7-6, 8-12
TSIZO-TSIZ2 signals, 7-11, 8-13
1TO-TT4 signals, 7-10, 8-13
u
UISA
definition, 1-19
registers, 2-2
Use of
IBA,
timing, 8-37
User instruction set architecture see UISA
Using DBWO, timing, 8-53 •
v
VEA
cache operation, 3-1
definition, 1-19
Vector offset table, exception, 4-3
Virtual environment architecture, see VEA
Index
w
WIMGbits
cache actions, 3-23
memory coherency, 8-29
WIM combination, 8-30
Write-back, 6-3, 6-12, 6-15
Write-through mode (W bit)
memory/cache access attriibute, 3-10
pelformance considerations, 6-16
Write-with-atomic operation, 3-20
Write-with-flush operation, 3-20
Write-with-kill operation, 3-20
WT
signal, 7-15
x
XA TS signal, 7-6, 8-38
XER register, 2-5
XFERDATA read/write operation, 3-22
111111
lndex-9