Complete Stage - IBM PowerPC 604 User Manual

6.2.1.1.5 Complete Stage
The complete stage maintains the correct architectural machine state.
In
doing this it
~onsiders
a number of instructions residing in the completion buffer and uses the
information about the status of instructions provided by the execute stage.
When instructions are dispatched, they are issued a position in the 16-entty completion
buffer which they hoid until they ineet the constraints of completion. When an instruction
finishes execution, its status is recorded in its completion buffer entty. The completion
buffer is managed as a first-in, first-out (FIFO) buffer; it examines the entries in the order
in which the instructions were dispatched. The fact that the completion buffer allows the
processor to retain the program order ensures that instructions are completed in order.
The status of four entries are examined during each cycle to determine whether the results
can be written back, and therefore, as many as four instructions can complete per clock. If
an instruction causes an exception, the status information in the completion buffer reflects
this, and this information in the completion buffer is used to generate the exception. In this
way the completion buffer is used
to
ensure a precise exception model. Typically,
exceptions are detected in the fetch, decode, or execute stage.
Apart from those restrictions necessary to support a precise exception model, the 604
imposes the following restrictions per each cycle:
• Completion stops before a store since store data is read directly from GPRs or FPRs
• Completion stops after a taken branch instruction to simplify the program counter
logic.
Note that the 604 decouples instruction completion from the actual update (write-back) of
the register file; therefore, instructions can complete regardless of how many registers they
must update, and a few instructions, such as load cache misses can complete before the
result is known. The write-back occurs during the complete stage if the ports and results are
available; otherwise, the write-back is treated as a separate stage, as shown in the timing
examples in Section 6.4.1, ''General Instruction Flow." This provision allows the processor
to complete instructions, without concern for the number or presence of results. Note that
if a read operation misses
in
the cache, the instruction can complete (as long as it is certain
that the instruction can cause no exceptions) even though the result is not available.
Rename buffer entries for the FPRs, GPRs, and
CR
act as temporary buffers for instructions
that have not completed and as write-back buffers for those that have. ·
Each of the rename buffers has two read ports for write-back, corresponding to the two
ports provided for write-back for the GPRs, FPRs, and CR.
As
many as two results are
copied from each write-back buffer to a register per clock cycle.
Chap._
6.
lnatruction Timing 6-11