IBM PowerPC 604 User Manual page 35

Major features of the 604 are as follows:
1-4
• High-performance, superscalar microprocessor
- As many as four instructions can be issued per clock cycle.
- As many as six instructions can start executing per clock (including three integer
instructions).
- Single clock cycle execution for most instructions
• Six independent execution units and two register files
- BPU featuring dynamic branch prediction
- Speculative execution through two branches
- 64-entry fully-associative branch target address cache (BTAC}
- 512-entry, direct-mapped branch history table (BHT) with two bits per entry
for four levels of prediction-not-taken, strongly not-taken, taken, strongly
taken
- Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU}
- Instructions that execute in the SCIU take one cycle to execute; most
instructions that execute in the MCIU take multiple cycles to execute.
- Each SCIU has a two-entry reservation station to minimize stalls.
- The MCIU has a two-entry reservation station and provides early exit (three
cycles) for 16- x 32-bit and overflow operations.
- Thirty-two GPRs for integer operands
- Twelve rename buffers for GPRs
- Three-stage floating-point unit (FPU)
- Fully IEEE 754-1985 compliant FPU for both single- and double-precision
operations
- Supports non-IEEE mode for time-critical operations
- Fully pipelined, single-pass double-precision design
- Hardware support for denormalized numbers
- Two-entry reservation station to minimize stalls
- Thirty-two 64-bit FPRs for single- or double-precision operands
- Load/store unit (LSU)
- Two-entry reservation station to minimize stalls
- Single-cycle, pipelined cache access
- Dedicated adder performs EA calculations
- Performs alignment and precision conversion for floating-point data
- Performs alignment and sign extension for integer data
PowerPC 604 RISC Microprocessor User's Manual