IBM PowerPC 604 User Manual page 72

Risc
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-
Implementation Note-Note that the 604 defines MSR[29] as the performance monitor
marked mode bit (PM). This additional bit is described in Table 2-1.
Bit
29
2-6
Table 2-1. MSR[PM] Bit
Name
Description
PM
Performance monitor marked mode
0
Process is not a marked process.
1
Process is a marked process.
This bit is specific to the 604, and is defined as reserved by the PowerPC architecture. For more
information
about
the performance monitor, see Chapter 9, "Performance Monitor."
- Processor version register (PVR). This register is a read-only register that
identifies the version (model) and revision level of the PowerPC processor.
For more information, see ''Processor Version Register (PVR)," in Chapter 2,
"PowerPC Register Set," of
The Programming Environments Manual.
Implementation Note-The processor version number is 4 for the 604. The
processor revision level starts at OxOOOO and is different for each revision of
the chip. The revision level is updated for each silicon revision.
-
Memory management registers
- Block-address translation (BAT) registers. The Power PC OEA includes eight
block-address translation registers (BATs), consisting of four pairs of
instruction BATs (IBATOU-IBAT3U and IBATOL-IBAT3L) and four pairs of
data BATs (DBATOU-DBAT3U and DBATOL-DBAT3L). See Figure 2-1 for
a list of the SPR numbers for the BAT registers. For more information, see
"BAT Registers," in Chapter 2, "PowerPC Register Set," of
The
Programming Environments Manual.
Because BAT upper and lower words
are loaded separately, software must ensure that BAT translations are correct
during the time that both BAT entries are being loaded.
- SDRl. The SDRl register specifies the page table base address used in
virtual-to-physical address translation. For more information, see "SDRl," in
Chapter 2, "PowerPC Register Set," of
The Programming Environments
Manual
for more information."
- Segment registers (SR). The PowerPC OEA defines sixteen 32-bit segment
registers
(SR~Rl5).
Note that the SRs are implemented on 32-bit
implementations only. The fields in the segment register are interpreted
differently depending on the value of bit 0. See "Segment Registers," in
Chapter 2, "PowerPC Register Set," of
The Programming Environments
Manual
for more information.
-
Exception handling registers
- Data address register (DAR). After a OSI or an alignment exception, DAR is
set to the effective address generated by the faulting instruction. See "Data
Address Register (DAR)," in Chapter 2, "Power PC Register Set," of
The
Programming Environments Manual
for more information.
PowerPC 604 RISC Microprocessor User"s Manual

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