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4.5.13 Performance Monitoring Interrupt (OxOOFOO)
The PowerPC 604 performance monitor is a software-accessible mechanism that provides
detailed information concerning the dispatch, execution, completion, and memory access
of PowerPC instructions. The performance monitor is provided to help system developers
to debug their systems and to increase system performance with efficient software,
especially in a multiprocessor system where memory hierarchy behavior must be
monitored and studied in order to develop algorithms that schedule tasks (and perhaps
partition them) and distribute data optimally.
The performance monitor uses the following SPRs:
•
Performance monitor counters 1 and 2 (PMCl and PMC2)-two 32-bit counters
used to store the number of times a certain event has occurred.
•
The monitor mode control register 0 (MMCRO), which establishes the function of
the counters.
•
Sampled instruction address and sampled data address registers (SIA and SDA). The
two address registers contain the addresses of the data and of the instruction that
caused a threshold-related performance monitor interrupt.
The 604 supports a performance monitor interrupt that is caused by a counter negative
condition or by a time-base flipped bit counter defined in the MMCRO register.
As with other PowerPC interrupts, the performance monitoring interrupt follows the
normal PowerPC exception model with a defined exception vector offset (OxOOFOO). The
priority of the performance monitoring interrupt is below the external interrupt and above
the decrementer interrupt. The contents of the SIA and SDA are described in
Section 2.1.2.4, "Performance Monitor Registers." The perf onnance monitor is described
in Chapter 9, "Performance Monitor."
4.5.14 Instruction Address Breakpoint Exception (Ox01300)
The instruction address breakpoint exception occurs when an attempt is made to execute an
instruction that matches the address in the instruction address breakpoint register (IABR)
and the breakpoint is enabled (IABR[30] is set). The instruction that triggers the instruction
address breakpoint exception is not executed before the exception handler is invoked. The
vector offset of the instruction address breakpoint exception is Ox01300.
4.5.15 System Management Interrupt (Ox01400)
The 604 implements a system management interrupt exception, which is not defined by the
PowerPC architecture. The system management exception is very similar to the external
interrupt exception and is particularly useful in implementing the nap mode. It has priority
over an external interrupt and it uses a different interrupt vector in the exception table (at
offset Ox01400).
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PowerPC 604 RISC Microprocessor User's Manual
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