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operation to a write-through page that hits a modified cache block in the cache
presents a coherency paradox to the processor. The 604 writes the data both to the
cache and to main memory (note that only the data for this store is written to main
memory and not the entire cache block). The state of the cache block is unchanged.
3.6.6 Coherency Paradoxes in Multiple-Processor Systems
It is possible to create a coherency paradox across multiple processors. Such paradoxes are
particularly difficult
to
handle since some scenarios could result in the purging of modified
data, and others may lead to unforeseen bus deadlocks.
Most of these paradoxes center around the interprocessor coherency of the memory
coherency bit (or the M bit). Improper use of this bit can lead to multiple processors
accepting a cache block into their caches and marking the data as exclusive. In turn, this
can lead
to
a state where the same cache block is modified in multiple processor caches.
Additional information on what bus operations are generated for the various instructions
and state conditions can be found in Chapter 8, "System Interface Operation."
3. 7 Cache Configuration
There are several bits in the HIDO register that can be used to configure the instruction and
data cache. These are described as follows:
•
Bit 1-Enable cache parity checking. Enables a machine check exception based on
the detection of a cache parity error. If this bit is cleared, cache parity errors are
ignored. Note that the machine check exception is further affected by the MSR[ME]
bit, which specifies whether the processor enters checkstop state or continues
processing.
•
Bit 7-Disable snoop response high state restore. If this bit is set, the processor
cannot drive the SHD and ARTRY signals to the high (negated) state, and the system
must restore the signals to the high state. See Chapter 7, "Signal Descriptions," for
more information.
•
Bit 16-Instruction cache enable. If this bit is cleared, the instruction cache is
neither accessed nor updated. Disabling the caches forces all pages to
be
accessed
as if they were marked cache-inhibited (WIM
=
XlX). All potential cache accesses
from the bus are ignored.
•
Bit 17-Data cache enable. If this bit is cleared, the data cache is neither accessed
nor updated. Disabling the cache forces all pages to be accessed as if they were
marked cache-inhibited (WIM
=
XlX). All potential cache accesses from the bus,
such as snoop and cache operations are ignored.
•
Bit 18-Instruction cache lock. Setting this bit locks the instruction cache, in which
case all cache misses are treated as cache-inhibited. Cache hits occur as normal.
Cache operations and the icbi instruction continue to work as normal.
Chapter 3. Cache and Bus Interface Unit Operation
3·15
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