Direct-Store Operation Timing - IBM PowerPC 604 User Manual

System designers should note the following:
• "Misplaced" reply operations (that match the processor tag and arrive unexpectedly)
are ignored by the 604.
• External logic must assert AACK for the 604, even though it is the receiver of the
reply operation. AACK is an input-only signal to the 604.
• The 604 monitors address parity when enabled by software and XATS and reply
operations (load or store).
8.6.4 Direct-Store Operation Timing
The following timing diagrams show the sequence of events in a typical 604 direct-store
load access (Figure 8-26) and a typical 604 direct-store store access (Figure 8-27). All
arbitration signals except for ABB and DBB have been omitted for clarity, although they
are still required as described earlier in this chapter. Note that, for either case, the number
of immediate operations depends on the amount and the alignment of
data
to be transferred.
If no more than 4 bytes are being transferred, and the data is double-word-aligned (that is,
does not straddle an 8-byte address boundary), there will be no immediate operation as
shown in the figures.
The 604 can transfer as many as 128 bytes of data in one load or store instruction (requiring
more than 33 immediate operations in the case of misaligned operands).
In Figure 8-26, XATS is
asserted
with the same timing relationship as TS in a memory
access. Notice, however, that the address bus (and XATC) transition on the next bus clock
cycle. The first of the two beats on the address bus is valid for one bus clock cycle window
only, and that window is defined by the assertion of XATS. The second address bus beat,
however, can be extended by delaying the assertion of AACK until the system has latched
the address.
The load request and load reply operations, shown in Figure 8-26, are address-only
transactions as denoted by the negated TT3 signal during their respective address tenures.
Note that other
types
of bus operations can occur between the individual direct-store
operations on the bus. The 604 involved in this transaction, however, does not initiate any
other direct-store load or store operations once the first direct-store operation has begun
address tenure; however, if the 1/0 operation is retried, other higher-priority operations can
occur.
Notice that, in this example (zero wait states), 13 bus clock cycles are required to transfer
no more than 8 bytes of data.
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PowerPC 804 RISC Microprocessor User's Manual